Allow csr mtvec to not have reset values
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@ -312,7 +312,8 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio
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val base = Reg(UInt(2 bits)) init(U"01") allowUnsetRegToAvoidLatch
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val extensions = Reg(Bits(26 bits)) init(misaExtensionsInit) allowUnsetRegToAvoidLatch
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}
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val mtvec = RegInit(U(mtvecInit,xlen bits)) allowUnsetRegToAvoidLatch
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val mtvec = Reg(UInt(xlen bits)).allowUnsetRegToAvoidLatch
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if(mtvecInit != null) mtvec init(mtvecInit)
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val mepc = Reg(UInt(xlen bits))
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val mstatus = new Area{
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val MIE, MPIE = RegInit(False)
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