Allow csr mtvec to not have reset values

This commit is contained in:
Dolu1990 2018-04-24 23:33:48 +02:00
parent a9cbc48eb2
commit cfc324aa0f
1 changed files with 2 additions and 1 deletions

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@ -312,7 +312,8 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio
val base = Reg(UInt(2 bits)) init(U"01") allowUnsetRegToAvoidLatch val base = Reg(UInt(2 bits)) init(U"01") allowUnsetRegToAvoidLatch
val extensions = Reg(Bits(26 bits)) init(misaExtensionsInit) allowUnsetRegToAvoidLatch val extensions = Reg(Bits(26 bits)) init(misaExtensionsInit) allowUnsetRegToAvoidLatch
} }
val mtvec = RegInit(U(mtvecInit,xlen bits)) allowUnsetRegToAvoidLatch val mtvec = Reg(UInt(xlen bits)).allowUnsetRegToAvoidLatch
if(mtvecInit != null) mtvec init(mtvecInit)
val mepc = Reg(UInt(xlen bits)) val mepc = Reg(UInt(xlen bits))
val mstatus = new Area{ val mstatus = new Area{
val MIE, MPIE = RegInit(False) val MIE, MPIE = RegInit(False)