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Pradeep2004 2021-04-30 22:35:41 +02:00 committed by GitHub
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@ -12,8 +12,14 @@ The BSCANE2 allows access between the internal FPGA logic and the JTAG Boundary
• After cloning all the files from https://github.com/SpinalHDL/VexRiscv, go to this path : src/main/scala/vexriscv/demo and find the Murax.scala file. • After cloning all the files from https://github.com/SpinalHDL/VexRiscv, go to this path : src/main/scala/vexriscv/demo and find the Murax.scala file.
• Comment out these lines to remove the toplevel jtag I/O pins: • Comment out the following lines to remove the toplevel jtag I/O pins in Murax.scala file
Line 165, Line 395 to 397, Line 410 to 403 val jtag = slave(Jtag())
val jtagClkBuffer = SB_GB()
jtagClkBuffer.USER_SIGNAL_TO_GLOBAL_BUFFER <> io.jtag_tck
jtagClkBuffer.GLOBAL_BUFFER_OUTPUT <> murax.io.jtag.tck
murax.io.jtag.tdi <> io.jtag_tdi
murax.io.jtag.tdo <> io.jtag_tdo
murax.io.jtag.tms <> io.jtag_tms
• In the Murax.scala file, delete line number 253 and add the following lines : • In the Murax.scala file, delete line number 253 and add the following lines :
val jtagCtrl = JtagTapInstructionCtrl() val jtagCtrl = JtagTapInstructionCtrl()