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Update GCC prebuild instructions for sifive.com reorg

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banahogg 2020-11-14 17:31:50 -08:00 committed by GitHub
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@ -412,7 +412,7 @@ Note that VexRiscv can run Linux on both cache full and cache less design.
A prebuild GCC toolsuite can be found here:
- https://www.sifive.com/products/tools/ => SiFive GNU Embedded Toolchain
- https://www.sifive.com/software/ => Prebuilt RISC‑V GCC Toolchain and Emulator
The VexRiscvSocSoftware makefiles are expecting to find this prebuild version in /opt/riscv/__contentOfThisPreBuild__