caches: work without writeBack stage
In the case of an MMU miss, the data caches will create a retry branch port. These currently implicitly go into the memory/writeBack stage, however not all CPUs have this stage. Place the retry branch port into the correct stage. Signed-off-by: Sean Cross <sean@xobs.io>
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@ -143,7 +143,7 @@ class DBusCachedPlugin(config : DataCacheConfig,
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decoderService.add(FENCE, Nil)
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decoderService.add(FENCE, Nil)
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mmuBus = pipeline.service(classOf[MemoryTranslator]).newTranslationPort(MemoryTranslatorPort.PRIORITY_DATA ,memoryTranslatorPortConfig)
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mmuBus = pipeline.service(classOf[MemoryTranslator]).newTranslationPort(MemoryTranslatorPort.PRIORITY_DATA ,memoryTranslatorPortConfig)
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redoBranch = pipeline.service(classOf[JumpService]).createJumpInterface(pipeline.writeBack)
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redoBranch = pipeline.service(classOf[JumpService]).createJumpInterface(if(pipeline.writeBack != null) pipeline.writeBack else pipeline.execute)
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if(catchSomething)
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if(catchSomething)
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exceptionBus = pipeline.service(classOf[ExceptionService]).newExceptionPort(pipeline.writeBack)
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exceptionBus = pipeline.service(classOf[ExceptionService]).newExceptionPort(pipeline.writeBack)
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@ -309,7 +309,7 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false,
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if(memoryTranslatorPortConfig != null) {
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if(memoryTranslatorPortConfig != null) {
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mmuBus = pipeline.service(classOf[MemoryTranslator]).newTranslationPort(MemoryTranslatorPort.PRIORITY_DATA, memoryTranslatorPortConfig)
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mmuBus = pipeline.service(classOf[MemoryTranslator]).newTranslationPort(MemoryTranslatorPort.PRIORITY_DATA, memoryTranslatorPortConfig)
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redoBranch = pipeline.service(classOf[JumpService]).createJumpInterface(pipeline.memory)
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redoBranch = pipeline.service(classOf[JumpService]).createJumpInterface(if(pipeline.memory != null) pipeline.memory else pipeline.execute)
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}
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}
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}
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}
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