Add jtag and vhdl option
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@ -1,8 +1,10 @@
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package vexriscv.demo
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import spinal.core._
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import spinal.lib._
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import spinal.lib.bus.avalon.AvalonMM
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import spinal.lib.com.jtag.Jtag
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import spinal.lib.eda.altera.{InterruptReceiverTag, QSysify, ResetEmitterTag}
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import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig}
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import vexriscv.plugin._
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@ -15,11 +17,11 @@ import vexriscv.{VexRiscv, VexRiscvConfig, plugin}
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//
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//}
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//make clean run DBUS=CACHED_AVALON IBUS=CACHED_AVALON MMU=no CSR=no DEBUG_PLUGIN=AVALON
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//make clean run DBUS=SIMPLE_AHBLITE3 IBUS=SIMPLE_AHBLITE3 MMU=no CSR=no DEBUG_PLUGIN=STD
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object VexRiscvAhbLite3ForSim{
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object VexRiscvAhbLite3{
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def main(args: Array[String]) {
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val report = SpinalVerilog{
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val report = SpinalConfig(mode = if(args.contains("--vhdl")) VHDL else Verilog).generate{
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//CPU configuration
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val cpuConfig = VexRiscvConfig(
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@ -157,16 +159,11 @@ object VexRiscvAhbLite3ForSim{
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// .setName("dBusAvalon")
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// .addTag(ClockDomainTag(ClockDomain.current))
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// }
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// case plugin: DebugPlugin => plugin.debugClockDomain {
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// plugin.io.bus.setAsDirectionLess()
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// slave(plugin.io.bus.fromAvalon())
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// .setName("debugBusAvalon")
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// .addTag(ClockDomainTag(plugin.debugClockDomain))
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// .parent = null //Avoid the io bundle to be interpreted as a QSys conduit
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// plugin.io.resetOut
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// .addTag(ResetEmitterTag(plugin.debugClockDomain))
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// .parent = null //Avoid the io bundle to be interpreted as a QSys conduit
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// }
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case plugin: DebugPlugin if args.contains("--jtag")=> plugin.debugClockDomain {
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plugin.io.bus.setAsDirectionLess()
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val jtag = slave(new Jtag()).setName("jtag")
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jtag <> plugin.io.bus.fromJtag()
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}
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case _ =>
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}
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}
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