Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Add jtag and vhdl option

This commit is contained in:
Dolu1990 2019-04-15 11:01:51 +02:00
parent ad27007c3c
commit d2b324e32b
1 changed files with 10 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
src/main/scala/vexriscv/demo/VexRiscvAhbLite3ForSim.scala → src/main/scala/vexriscv/demo/VexRiscvAhbLite3.scala
View File

@ -1,8 +1,10 @@
package vexriscv.demo package vexriscv.demo
import spinal.core._ import spinal.core._
import spinal.lib._ import spinal.lib._
import spinal.lib.bus.avalon.AvalonMM import spinal.lib.bus.avalon.AvalonMM
import spinal.lib.com.jtag.Jtag
import spinal.lib.eda.altera.{InterruptReceiverTag, QSysify, ResetEmitterTag} import spinal.lib.eda.altera.{InterruptReceiverTag, QSysify, ResetEmitterTag}
import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig} import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig}
import vexriscv.plugin._ import vexriscv.plugin._
@ -15,11 +17,11 @@ import vexriscv.{VexRiscv, VexRiscvConfig, plugin}
// //
//} //}
//make clean run DBUS=CACHED_AVALON IBUS=CACHED_AVALON MMU=no CSR=no DEBUG_PLUGIN=AVALON //make clean run DBUS=SIMPLE_AHBLITE3 IBUS=SIMPLE_AHBLITE3 MMU=no CSR=no DEBUG_PLUGIN=STD
object VexRiscvAhbLite3ForSim{ object VexRiscvAhbLite3{
def main(args: Array[String]) { def main(args: Array[String]) {
val report = SpinalVerilog{ val report = SpinalConfig(mode = if(args.contains("--vhdl")) VHDL else Verilog).generate{
//CPU configuration //CPU configuration
val cpuConfig = VexRiscvConfig( val cpuConfig = VexRiscvConfig(
@ -157,16 +159,11 @@ object VexRiscvAhbLite3ForSim{
// .setName("dBusAvalon") // .setName("dBusAvalon")
// .addTag(ClockDomainTag(ClockDomain.current)) // .addTag(ClockDomainTag(ClockDomain.current))
// } // }
// case plugin: DebugPlugin => plugin.debugClockDomain { case plugin: DebugPlugin if args.contains("--jtag")=> plugin.debugClockDomain {
// plugin.io.bus.setAsDirectionLess() plugin.io.bus.setAsDirectionLess()
// slave(plugin.io.bus.fromAvalon()) val jtag = slave(new Jtag()).setName("jtag")
// .setName("debugBusAvalon") jtag <> plugin.io.bus.fromJtag()
// .addTag(ClockDomainTag(plugin.debugClockDomain)) }
// .parent = null //Avoid the io bundle to be interpreted as a QSys conduit
// plugin.io.resetOut
// .addTag(ResetEmitterTag(plugin.debugClockDomain))
// .parent = null //Avoid the io bundle to be interpreted as a QSys conduit
// }
case _ => case _ =>
} }
} }