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Merge pull request #145 from zeldin/bigendian2 

Update big endian instruction encoding
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Dolu1990 2020-10-21 12:56:56 +02:00 committed by GitHub
parent 98de02051e 6c8e97f825
commit d490f903ea
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1 changed files with 2 additions and 3 deletions
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src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
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@ -373,10 +373,9 @@ class IBusSimplePlugin( resetVector : BigInt,
fetchRsp.rsp := rspBuffer.output.payload fetchRsp.rsp := rspBuffer.output.payload
fetchRsp.rsp.error.clearWhen(!rspBuffer.output.valid) //Avoid interference with instruction injection from the debug plugin fetchRsp.rsp.error.clearWhen(!rspBuffer.output.valid) //Avoid interference with instruction injection from the debug plugin
if(bigEndian){ if(bigEndian){
// inst(15 downto 0) should contain lower addressed parcel, // instructions are stored in little endian byteorder
// and inst(31 downto 16) the higher addressed parcel
fetchRsp.rsp.inst.allowOverride fetchRsp.rsp.inst.allowOverride
fetchRsp.rsp.inst := rspBuffer.output.payload.inst.rotateLeft(16) fetchRsp.rsp.inst := EndiannessSwap(rspBuffer.output.payload.inst)
} }
val join = Stream(FetchRsp()) val join = Stream(FetchRsp())