Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #145 from zeldin/bigendian2 

Update big endian instruction encoding
This commit is contained in:
Dolu1990 2020-10-21 12:56:56 +02:00 committed by GitHub
parent 98de02051e 6c8e97f825
commit d490f903ea
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 2 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
View File

@ -373,10 +373,9 @@ class IBusSimplePlugin( resetVector : BigInt,
fetchRsp.rsp := rspBuffer.output.payload
fetchRsp.rsp.error.clearWhen(!rspBuffer.output.valid) //Avoid interference with instruction injection from the debug plugin
if(bigEndian){
// inst(15 downto 0) should contain lower addressed parcel,
// and inst(31 downto 16) the higher addressed parcel
// instructions are stored in little endian byteorder
fetchRsp.rsp.inst.allowOverride
fetchRsp.rsp.inst := rspBuffer.output.payload.inst.rotateLeft(16)
fetchRsp.rsp.inst := EndiannessSwap(rspBuffer.output.payload.inst)
}
val join = Stream(FetchRsp())