mirror of
https://github.com/SpinalHDL/VexRiscv.git
synced 2025-01-03 03:43:39 -05:00
Remap Briey/Murax onChipRam to 0x80000000 to avoid having memory at the null pointer location
Commit missing file Update dhrystone hex to use GP. 1.44 DMIPS/Mhz
This commit is contained in:
Dolu1990
parent
4729e46763
commit
d4b05ea365
23 changed files with 11419 additions and 201653 deletions
16
README.md
16
README.md
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@ -21,7 +21,7 @@ This repository host an RISC-V implementation written in SpinalHDL. There is som
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- RV32IM instruction set
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- Pipelined on 5 stages (Fetch, Decode, Execute, Memory, WriteBack)
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- 1.40 DMIPS/Mhz when all features are enabled
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- 1.44 DMIPS/Mhz when all features are enabled
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- Optimized for FPGA, fully portable
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- AXI4 and Avalon ready
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- Optional MUL/DIV extension
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@ -49,13 +49,13 @@ All the cached configuration have some cache trashing during the dhrystone bench
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The used CPU corresponding configuration can be find in src/scala/vexriscv/demo.
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```
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VexRiscv smallest (RV32I, 0.51 DMIPS/Mhz, no datapath bypass, no interrupt) ->
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VexRiscv smallest (RV32I, 0.52 DMIPS/Mhz, no datapath bypass, no interrupt) ->
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Artix 7 -> 346 Mhz 481 LUT 539 FF
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Cyclone V -> 201 Mhz 347 ALMs
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Cyclone IV -> 190 Mhz 673 LUT 529 FF
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Cyclone II -> 154 Mhz 673 LUT 528 FF
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VexRiscv smallest (RV32I, 0.51 DMIPS/Mhz, no datapath bypass) ->
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VexRiscv smallest (RV32I, 0.52 DMIPS/Mhz, no datapath bypass) ->
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Artix 7 -> 340 Mhz 562 LUT 589 FF
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Cyclone V -> 202 Mhz 387 ALMs
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Cyclone IV -> 180 Mhz 780 LUT 579 FF
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@ -67,31 +67,31 @@ VexRiscv small and productive (RV32I, 0.82 DMIPS/Mhz) ->
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Cyclone IV -> 147 Mhz 1,062 LUT 552 FF
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Cyclone II -> 120 Mhz 1,072 LUT 551 FF
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VexRiscv full no cache (RV32IM, 1.20 DMIPS/Mhz, single cycle barrel shifter, debug module, catch exceptions, static branch) ->
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VexRiscv full no cache (RV32IM, 1.22 DMIPS/Mhz, single cycle barrel shifter, debug module, catch exceptions, static branch) ->
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Artix 7 -> 310 Mhz 1391 LUT 934 FF
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Cyclone V -> 143 Mhz 935 ALMs
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Cyclone IV -> 123 Mhz 1,916 LUT 960 FF
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Cyclone II -> 108 Mhz 1,939 LUT 959 FF
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VexRiscv full (RV32IM, 1.13 DMIPS/Mhz with cache trashing, 4KB-I$,4KB-D$, single cycle barrel shifter, debug module, catch exceptions, static branch) ->
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VexRiscv full (RV32IM, 1.21 DMIPS/Mhz with cache trashing, 4KB-I$,4KB-D$, single cycle barrel shifter, debug module, catch exceptions, static branch) ->
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Artix 7 -> 250 Mhz 1911 LUT 1501 FF
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Cyclone V -> 132 Mhz 1,266 ALMs
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Cyclone IV -> 127 Mhz 2,733 LUT 1,762 FF
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Cyclone II -> 103 Mhz 2,791 LUT 1,760 FF
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VexRiscv full max perf -> (RV32IM, 1.40 DMIPS/Mhz, 16KB-I$,16KB-D$, single cycle barrel shifter, debug module, catch exceptions, dynamic branch prediction in the fetch stage, branch and shift operations done in the Execute stage) ->
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VexRiscv full max perf -> (RV32IM, 1.44 DMIPS/Mhz, 16KB-I$,16KB-D$, single cycle barrel shifter, debug module, catch exceptions, dynamic branch prediction in the fetch stage, branch and shift operations done in the Execute stage) ->
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Artix 7 -> 198 Mhz 1920 LUT 1528 FF
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Cyclone V -> 90 Mhz 1,261 ALMs
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Cyclone IV -> 88 Mhz 2,780 LUT 1,788 FF
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VexRiscv full with MMU (RV32IM, 1.17 DMIPS/Mhz with cache trashing, 4KB-I$, 4KB-D$, single cycle barrel shifter, debug module, catch exceptions, dynamic branch, MMU) ->
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VexRiscv full with MMU (RV32IM, 1.26 DMIPS/Mhz with cache trashing, 4KB-I$, 4KB-D$, single cycle barrel shifter, debug module, catch exceptions, dynamic branch, MMU) ->
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Artix 7 -> 223 Mhz 2085 LUT 2020 FF
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Cyclone V -> 110 Mhz 1,503 ALMs
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Cyclone IV -> 108 Mhz 3,153 LUT 2,281 FF
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Cyclone II -> 94 Mhz 3,187 LUT 2,281 FF
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```
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There is a summary of the configuration which produce 1.40 DMIPS :
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There is a summary of the configuration which produce 1.44 DMIPS :
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- 5 stage : F -> D -> E -> M -> WB
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- single cycle ADD/SUB/Bitwise/Shift ALU
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Binary file not shown.
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@ -1,76 +1,77 @@
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:0200000480007A
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:100000006F00000B1300000013000000130000003D
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:100010001300000013000000130000001300000094
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:10002000232E11FE232C51FE232A61FE232871FE6C
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:100030002326A1FE2324B1FE2322C1FE2320D1FECC
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:10004000232EE1FC232CF1FC232A01FD232811FDA2
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:100050002326C1FD2324D1FD2322E1FD2320F1FD30
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:10006000130101FCEF00403B8320C1038322810385
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:10006000130101FCEF00403A8320C1038322810386
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:1000700003234103832301030325C1028325810256
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:1000800003264102832601020327C1018327810140
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:100090000328410183280101032EC100832E810022
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:1000A000032F4100832F010013010104730020304E
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:1000B000170100001301017F130540011300000028
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:1000C00013000000130000001305F5FFE31805FE00
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:1000D000170500001305453C970500009385C53BB7
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:1000E0006308B50023200500130545006FF05FFF8E
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:1000F000170500001305453A1301C1FF97050000DD
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:1001000093858539630EB5008326050013054500E8
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:100110002320A100E7800600032501006FF01FFEE9
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:100120001301410037150000130505887310453091
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:100130001305800073100530EF00C0196F00000038
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:10014000130101FE232E8100130401022326A4FEC5
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:100150008327C4FE23A007008327C4FE23A407002F
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:10016000130000000324C101130101026780000095
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:10017000130101FE232E8100130401022326A4FE95
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:10018000130000000324C101130101026780000075
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:10019000130101FE232E8100130401022326A4FE75
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:1001A0008327C4FE23A207008327C4FE1307F0FFA2
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:1001B00023A0E700130000000324C1011301010282
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:1001C00067800000130101FE232E81001304010249
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:1001D0002326A4FE8327C4FE83A7470093D70701E5
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:1001E00093F7F70F138507000324C10113010102E0
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:1001F00067800000130101FE232E81001304010219
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:100200002326A4FE8327C4FE83A7470093D7870134
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:10021000138507000324C101130101026780000058
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:10022000130101FE232E1100232C8100130401026F
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:100230002326A4FE2324B4FE130000000325C4FEDD
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:10024000EFF05FF893070500E38A07FE8327C4FEFB
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:10025000032784FE23A0E700130000008320C101D0
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:10026000032481011301010267800000130101FED4
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:10027000232E8100130401022326A4FE2324B4FEAE
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:10028000832784FE03A7C7008327C4FE23A4E700B7
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:10029000832784FE83A707001387F7FF832784FE45
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:1002A00083A74700939787003367F700832784FE6F
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:1002B00083A78700939707013367F7008327C4FE5E
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:1002C00023A6E700130000000324C101130101026B
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:1002D00067800000130101FD2326110223248102FF
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:1002E00013040103930710002322F4FE9307200058
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:1002F0002320F4FE93073000232EF4FC232604FE73
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:10030000B70702F013850701EFF09FE8370502F009
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:10031000EFF01FE6B70702F013850704EFF05FE286
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:10032000B70702F0373700001307F7ED23A0E70007
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:10033000B70702F0938707041307703E23A2E70074
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:10034000B70702F093870704370701001307270058
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:1003500023A0E700B70702F0938707011307F00017
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:1003600023A0E700B70702F09387070113071000E7
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:1003700023A2E700B70700F01307F00F23A4E7005C
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:10038000B70700F023A20700B70701F0130720000A
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:1003900023A2E700B70701F01307100423A0E7002A
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:1003A000832744FE0327C4FEB307F7002326F4FE89
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:1003B000032704FE8327C4FDB307F7000327C4FE09
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:1003C000B307F7002326F4FE232404FE6F00000188
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:1003D000832784FE938717002324F4FE032784FEDB
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:1003E000B7C700009387F734E3F4E7FEB70700F0E0
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:1003F00083A7470093F607FCB70700F083A74700E1
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:100400009387170013F7F703B70700F033E7E60009
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:1004100023A2E7006FF0DFF8130101FF232681001C
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:1004200013040101B70702F09387070183A70700B0
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:1004300093F7170063800704B70700F003A747008E
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:10044000B70700F01347070823A2E700B70702F039
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:10045000938707011307100023A0E7006F008001B6
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:10046000B70701F003A70700B70701F01377F70FED
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:1004700023A0E700B70701F083A7470093F7072001
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:10048000E39007FE130000000324C10013010101E3
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:040490006780000081
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:04000003000000B049
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:1000B00097110000938181BD138181A01705000075
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:1000C0001305C53C970500009385453C6308B500C2
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:1000D00023200500130545006FF05FFF17050000A2
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:1000E0001305853A1301C1FF970500009385C539B3
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:1000F000630EB50083260500130545002320A100EB
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:10010000E7800600032501006FF01FFE1301410088
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:10011000371500001305058873104530372500009A
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:100120001305858073100530EF00C0196F000000C3
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:10013000130101FE232E8100130401022326A4FED5
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:100140008327C4FE23A007008327C4FE23A407003F
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:10015000130000000324C1011301010267800000A5
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:10016000130101FE232E8100130401022326A4FEA5
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:10017000130000000324C101130101026780000085
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:10018000130101FE232E8100130401022326A4FE85
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:100190008327C4FE23A207008327C4FE1307F0FFB2
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:1001A00023A0E700130000000324C1011301010292
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:1001B00067800000130101FE232E81001304010259
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:1001C0002326A4FE8327C4FE83A7470093D70701F5
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:1001D00093F7F70F138507000324C10113010102F0
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:1001E00067800000130101FE232E81001304010229
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:1001F0002326A4FE8327C4FE83A7470093D7870145
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:10020000138507000324C101130101026780000068
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:10021000130101FE232E1100232C8100130401027F
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:100220002326A4FE2324B4FE130000000325C4FEED
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:10023000EFF05FF893070500E38A07FE8327C4FE0B
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:10024000032784FE23A0E700130000008320C101E0
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:10025000032481011301010267800000130101FEE4
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:10026000232E8100130401022326A4FE2324B4FEBE
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:10027000832784FE03A7C7008327C4FE23A4E700C7
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:10028000832784FE83A707001387F7FF832784FE55
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:1002900083A74700939787003367F700832784FE7F
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:1002A00083A78700939707013367F7008327C4FE6E
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:1002B00023A6E700130000000324C101130101027B
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:1002C00067800000130101FD23261102232481020F
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:1002D00013040103930710002322F4FE9307200068
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:1002E0002320F4FE93073000232EF4FC232604FE83
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:1002F000B70702F013850701EFF09FE8370502F01A
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:10030000EFF01FE6B70702F013850704EFF05FE296
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:10031000B70702F0373700001307F7ED23A0E70017
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:10032000B70702F0938707041307703E23A2E70084
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:10033000B70702F093870704370701001307270068
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:1003400023A0E700B70702F0938707011307F00027
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:1003500023A0E700B70702F09387070113071000F7
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:1003600023A2E700B70700F01307F00F23A4E7006C
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:10037000B70700F023A20700B70701F0130720001A
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:1003800023A2E700B70701F01307100423A0E7003A
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:10039000832744FE0327C4FEB307F7002326F4FE99
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:1003A000032704FE8327C4FDB307F7000327C4FE19
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:1003B000B307F7002326F4FE232404FE6F00000198
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:1003C000832784FE938717002324F4FE032784FEEB
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:1003D000B7C700009387F734E3F4E7FEB70700F0F0
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:1003E00083A7470093F607FCB70700F083A74700F1
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:1003F0009387170013F7F703B70700F033E7E6001A
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:1004000023A2E7006FF0DFF8130101FF232681002C
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:1004100013040101B70702F09387070183A70700C0
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:1004200093F7170063800704B70700F003A747009E
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:10043000B70700F01347070823A2E700B70702F049
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:10044000938707011307100023A0E7006F008001C6
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:10045000B70701F003A70700B70701F01377F70FFD
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:1004600023A0E700B70701F083A7470093F7072011
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:10047000E39007FE130000000324C10013010101F3
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:040480006780000091
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:040484000000000074
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:040000058000000077
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:00000001FF
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@ -88,6 +88,9 @@ object Riscv{
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def MRET = M"00110000001000000000000001110011"
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def WFI = M"00010000010100000000000001110011"
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def FENCE = M"-----------------000-----0001111"
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def FENCE_I = M"-----------------001-----0001111"
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object CSR{
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def MVENDORID = 0xF11 // MRO Vendor ID.
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def MARCHID = 0xF12 // MRO Architecture ID.
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@ -32,7 +32,7 @@ object TestsWorkspace {
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val configFull = VexRiscvConfig(
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plugins = List(
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new PcManagerSimplePlugin(
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resetVector = 0x00000000l,
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resetVector = 0x80000000l,
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relaxedPcCalculation = false
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),
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// new IBusSimplePlugin(
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@ -117,7 +117,7 @@ object TestsWorkspace {
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// new HazardSimplePlugin(false, false, false, false),
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new MulPlugin,
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new DivPlugin,
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new CsrPlugin(CsrPluginConfig.all),
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new CsrPlugin(CsrPluginConfig.all(0x80000020l)),
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new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))),
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new BranchPlugin(
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earlyBranch = true,
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@ -192,7 +192,7 @@ object TestsWorkspace {
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catchAddressMisaligned = true,
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catchAccessFault = true
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),
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new CsrPlugin(CsrPluginConfig.small),
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new CsrPlugin(CsrPluginConfig.small(0x80000020l)),
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new DecoderSimplePlugin(
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catchIllegalInstruction = true
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),
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@ -47,7 +47,7 @@ object BrieyConfig{
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rxFifoDepth = 16
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),
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cpuPlugins = ArrayBuffer(
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new PcManagerSimplePlugin(0x00000000l, false),
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new PcManagerSimplePlugin(0x80000000l, false),
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// new IBusSimplePlugin(
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// interfaceKeepData = false,
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// catchAccessFault = true
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@ -136,7 +136,7 @@ object BrieyConfig{
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misaExtensionsInit = 66,
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misaAccess = CsrAccess.NONE,
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mtvecAccess = CsrAccess.NONE,
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mtvecInit = 0x00000020l,
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mtvecInit = 0x80000020l,
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mepcAccess = CsrAccess.READ_WRITE,
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mscratchGen = false,
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mcauseAccess = CsrAccess.READ_ONLY,
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@ -309,7 +309,7 @@ class Briey(config: BrieyConfig) extends Component{
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val axiCrossbar = Axi4CrossbarFactory()
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axiCrossbar.addSlaves(
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ram.io.axi -> (0x00000000L, onChipRamSize),
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ram.io.axi -> (0x80000000L, onChipRamSize),
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sdramCtrl.io.axi -> (0x40000000L, sdramLayout.capacity),
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apbBridge.io.axi -> (0xF0000000L, 1 MB)
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)
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@ -6,7 +6,10 @@ object DhrystoneBench extends App{
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def doCmd(cmd : String) : String = {
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val stdOut = new StringBuilder()
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class Logger extends ProcessLogger {override def err(s: => String): Unit = {if(!s.startsWith("ar: creating ")) println(s)}
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override def out(s: => String): Unit = {stdOut ++= s}
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override def out(s: => String): Unit = {
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println(s)
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stdOut ++= s
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}
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override def buffer[T](f: => T) = f
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}
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Process(cmd, new File("src/test/cpp/regression")).!(new Logger)
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@ -16,8 +19,9 @@ object DhrystoneBench extends App{
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def getDmips(name : String, gen : => Unit, test : String): Unit ={
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gen
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val str = doCmd(test)
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assert(!str.contains("FAIL"))
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val intFind = "(\\d+\\.?)+".r
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val dmips = intFind.findFirstIn("DMIPS per Mhz\\: (\\d+.?)+".r.findAllIn(str).toList.last).get.toDouble
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val dmips = intFind.findFirstIn("DMIPS per Mhz\\: (\\d+.?)+".r.findAllIn(str).toList.last).get.toDouble
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report ++= name + " -> " + dmips + "\n"
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}
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@ -25,52 +29,52 @@ object DhrystoneBench extends App{
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getDmips(
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name = "GenSmallestNoCsr",
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gen = GenSmallestNoCsr.main(null),
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test = "make clean run REDO=0 IBUS=SIMPLE DBUS=SIMPLE CSR=no MMU=no DEBUG_PLUGIN=no MUL=no DIV=no"
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test = "make clean run REDO=10 IBUS=SIMPLE DBUS=SIMPLE CSR=no MMU=no DEBUG_PLUGIN=no MUL=no DIV=no"
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)
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getDmips(
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name = "GenSmallest",
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gen = GenSmallest.main(null),
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test = "make clean run REDO=0 IBUS=SIMPLE DBUS=SIMPLE CSR=no MMU=no DEBUG_PLUGIN=no MUL=no DIV=no"
|
||||
test = "make clean run REDO=10 IBUS=SIMPLE DBUS=SIMPLE CSR=no MMU=no DEBUG_PLUGIN=no MUL=no DIV=no"
|
||||
)
|
||||
|
||||
|
||||
getDmips(
|
||||
name = "GenSmallAndProductive",
|
||||
gen = GenSmallAndProductive.main(null),
|
||||
test = "make clean run REDO=0 IBUS=SIMPLE DBUS=SIMPLE CSR=no MMU=no DEBUG_PLUGIN=no MUL=no DIV=no"
|
||||
test = "make clean run REDO=10 IBUS=SIMPLE DBUS=SIMPLE CSR=no MMU=no DEBUG_PLUGIN=no MUL=no DIV=no"
|
||||
)
|
||||
|
||||
|
||||
getDmips(
|
||||
name = "GenFullNoMmuNoCache",
|
||||
gen = GenFullNoMmuNoCache.main(null),
|
||||
test = "make clean run REDO=0 IBUS=SIMPLE DBUS=SIMPLE MMU=no"
|
||||
test = "make clean run REDO=10 IBUS=SIMPLE DBUS=SIMPLE CSR=no MMU=no"
|
||||
)
|
||||
|
||||
getDmips(
|
||||
name = "GenNoCacheNoMmuMaxPerf",
|
||||
gen = GenNoCacheNoMmuMaxPerf.main(null),
|
||||
test = "make clean run REDO=0 MMU=no CSR=no DBUS=SIMPLE IBUS=SIMPLE"
|
||||
test = "make clean run REDO=10 MMU=no CSR=no DBUS=SIMPLE IBUS=SIMPLE"
|
||||
)
|
||||
|
||||
|
||||
getDmips(
|
||||
name = "GenFullNoMmuMaxPerf",
|
||||
gen = GenFullNoMmuMaxPerf.main(null),
|
||||
test = "make clean run REDO=0 MMU=no"
|
||||
test = "make clean run REDO=10 MMU=no CSR=no"
|
||||
)
|
||||
getDmips(
|
||||
name = "GenFullNoMmu",
|
||||
gen = GenFullNoMmu.main(null),
|
||||
test = "make clean run REDO=0 MMU=no "
|
||||
test = "make clean run REDO=10 MMU=no CSR=no"
|
||||
)
|
||||
|
||||
getDmips(
|
||||
name = "GenFull",
|
||||
gen = GenFull.main(null),
|
||||
test = "make clean run REDO=0"
|
||||
test = "make clean run REDO=10 CSR=no MMU=no"
|
||||
)
|
||||
|
||||
println(report)
|
||||
|
|
|
|||
67
src/main/scala/vexriscv/demo/GenDeterministicVex.scala
Normal file
67
src/main/scala/vexriscv/demo/GenDeterministicVex.scala
Normal file
|
|
@ -0,0 +1,67 @@
|
|||
package vexriscv.demo
|
||||
|
||||
import spinal.core._
|
||||
import vexriscv.plugin._
|
||||
import vexriscv.{VexRiscv, VexRiscvConfig, plugin}
|
||||
|
||||
/**
|
||||
* Created by spinalvm on 15.06.17.
|
||||
*/
|
||||
object GenDeterministicVex extends App{
|
||||
def cpu() = new VexRiscv(
|
||||
config = VexRiscvConfig(
|
||||
plugins = List(
|
||||
new PcManagerSimplePlugin(
|
||||
resetVector = 0x80000000l,
|
||||
relaxedPcCalculation = false
|
||||
),
|
||||
new IBusSimplePlugin(
|
||||
interfaceKeepData = false,
|
||||
catchAccessFault = true
|
||||
),
|
||||
new DBusSimplePlugin(
|
||||
catchAddressMisaligned = true,
|
||||
catchAccessFault = true,
|
||||
earlyInjection = false
|
||||
),
|
||||
new StaticMemoryTranslatorPlugin(
|
||||
ioRange = _(31 downto 28) === 0xF
|
||||
),
|
||||
new DecoderSimplePlugin(
|
||||
catchIllegalInstruction = true
|
||||
),
|
||||
new RegFilePlugin(
|
||||
regFileReadyKind = plugin.SYNC,
|
||||
zeroBoot = false
|
||||
),
|
||||
new IntAluPlugin,
|
||||
new SrcPlugin(
|
||||
separatedAddSub = false,
|
||||
executeInsertion = true
|
||||
),
|
||||
new FullBarrielShifterPlugin(earlyInjection = true),
|
||||
new HazardSimplePlugin(
|
||||
bypassExecute = true,
|
||||
bypassMemory = true,
|
||||
bypassWriteBack = true,
|
||||
bypassWriteBackBuffer = true,
|
||||
pessimisticUseSrc = false,
|
||||
pessimisticWriteRegFile = false,
|
||||
pessimisticAddressMatch = false
|
||||
),
|
||||
new MulPlugin,
|
||||
new DivPlugin,
|
||||
new CsrPlugin(CsrPluginConfig.small),
|
||||
new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))),
|
||||
new BranchPlugin(
|
||||
earlyBranch = true,
|
||||
catchAddressMisaligned = true,
|
||||
prediction = STATIC
|
||||
),
|
||||
new YamlPlugin("cpu0.yaml")
|
||||
)
|
||||
)
|
||||
)
|
||||
|
||||
SpinalVerilog(cpu())
|
||||
}
|
||||
|
|
@ -53,7 +53,7 @@ object MuraxConfig{
|
|||
gpioWidth = 32,
|
||||
cpuPlugins = ArrayBuffer( //DebugPlugin added by the toplevel
|
||||
new PcManagerSimplePlugin(
|
||||
resetVector = 0x00000000l,
|
||||
resetVector = 0x80000000l,
|
||||
relaxedPcCalculation = true
|
||||
),
|
||||
new IBusSimplePlugin(
|
||||
|
|
@ -65,7 +65,7 @@ object MuraxConfig{
|
|||
catchAccessFault = false,
|
||||
earlyInjection = false
|
||||
),
|
||||
new CsrPlugin(CsrPluginConfig.smallest),
|
||||
new CsrPlugin(CsrPluginConfig.smallest(mtvecInit = 0x80000020l)),
|
||||
new DecoderSimplePlugin(
|
||||
catchIllegalInstruction = false
|
||||
),
|
||||
|
|
@ -278,7 +278,7 @@ case class Murax(config : MuraxConfig) extends Component{
|
|||
val logic = new MuraxSimpleBusDecoder(
|
||||
master = mainBusArbiter.io.masterBus,
|
||||
specification = List[(SimpleBus,SizeMapping)](
|
||||
ram.io.bus -> (0x00000000l, onChipRamSize kB),
|
||||
ram.io.bus -> (0x80000000l, onChipRamSize kB),
|
||||
apbBridge.io.simpleBus -> (0xF0000000l, 1 MB)
|
||||
),
|
||||
pipelineMaster = pipelineMainBus
|
||||
|
|
|
|||
|
|
@ -112,6 +112,7 @@ class MuraxSimpleBusRam(onChipRamSize : BigInt, onChipRamHexFile : String, simpl
|
|||
case 4 =>
|
||||
offset = hToI(line, 9, 4) << 16
|
||||
case 3 =>
|
||||
case 5 =>
|
||||
case 1 =>
|
||||
}
|
||||
}
|
||||
|
|
@ -120,7 +121,8 @@ class MuraxSimpleBusRam(onChipRamSize : BigInt, onChipRamHexFile : String, simpl
|
|||
|
||||
val initContent = Array.fill[BigInt](ram.wordCount)(0)
|
||||
readHexFile(onChipRamHexFile,(address,data) => {
|
||||
initContent(address >> 2) |= BigInt(data) << ((address & 3)*8)
|
||||
val addressWithoutOffset = address + Int.MinValue
|
||||
initContent(addressWithoutOffset >> 2) |= BigInt(data) << ((addressWithoutOffset & 3)*8)
|
||||
})
|
||||
ram.initBigInt(initContent)
|
||||
}
|
||||
|
|
|
|||
96
src/test/cpp/regression/debug.gtkw
Normal file
96
src/test/cpp/regression/debug.gtkw
Normal file
|
|
@ -0,0 +1,96 @@
|
|||
[*]
|
||||
[*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI
|
||||
[*] Thu Feb 1 00:52:25 2018
|
||||
[*]
|
||||
[dumpfile] "/home/spinalvm/hdl/VexRiscv/src/test/cpp/regression/rv32ui-p-lui.vcd"
|
||||
[dumpfile_mtime] "Thu Feb 1 00:52:17 2018"
|
||||
[dumpfile_size] 183735
|
||||
[savefile] "/home/spinalvm/hdl/VexRiscv/src/test/cpp/regression/debug.gtkw"
|
||||
[timestart] 0
|
||||
[size] 1784 950
|
||||
[pos] -1 -1
|
||||
*-3.000000 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
||||
[treeopen] TOP.
|
||||
[treeopen] TOP.VexRiscv.
|
||||
[sst_width] 409
|
||||
[signals_width] 540
|
||||
[sst_expanded] 1
|
||||
[sst_vpaned_height] 271
|
||||
@22
|
||||
TOP.VexRiscv.prefetch_PcManagerSimplePlugin_jump_pcLoad_payload[31:0]
|
||||
@28
|
||||
TOP.VexRiscv.prefetch_PcManagerSimplePlugin_jump_pcLoad_valid
|
||||
@22
|
||||
TOP.VexRiscv.prefetch_PC[31:0]
|
||||
@28
|
||||
TOP.VexRiscv.debug_bus_cmd_valid
|
||||
TOP.VexRiscv.reset
|
||||
TOP.VexRiscv.clk
|
||||
TOP.VexRiscv.prefetch_PcManagerSimplePlugin_samplePcNext
|
||||
@22
|
||||
TOP.VexRiscv.prefetch_PcManagerSimplePlugin_pcBeforeJumps[31:0]
|
||||
@28
|
||||
TOP.VexRiscv.prefetch_PcManagerSimplePlugin_jump_pcLoad_valid
|
||||
TOP.VexRiscv.fetch_BranchPlugin_hit
|
||||
TOP.VexRiscv.execute_BRANCH_DO
|
||||
@22
|
||||
TOP.VexRiscv.prefetch_PcManagerSimplePlugin_pcReg[31:0]
|
||||
TOP.VexRiscv.prefetch_PcManagerSimplePlugin_pc[31:0]
|
||||
@28
|
||||
TOP.VexRiscv.prefetch_arbitration_isValid
|
||||
TOP.VexRiscv.fetch_arbitration_isValid
|
||||
TOP.VexRiscv.decode_arbitration_isValid
|
||||
TOP.VexRiscv.execute_arbitration_isValid
|
||||
TOP.VexRiscv.memory_arbitration_isValid
|
||||
TOP.VexRiscv.writeBack_arbitration_isValid
|
||||
TOP.VexRiscv.CsrPlugin_interrupt
|
||||
TOP.VexRiscv.CsrPlugin_exception
|
||||
TOP.VexRiscv.decode_arbitration_isStuck
|
||||
TOP.VexRiscv.decode_arbitration_isStuckByOthers
|
||||
TOP.VexRiscv.execute_arbitration_isStuck
|
||||
TOP.VexRiscv.execute_arbitration_isStuckByOthers
|
||||
TOP.VexRiscv.fetch_arbitration_isStuck
|
||||
TOP.VexRiscv.fetch_arbitration_isStuckByOthers
|
||||
TOP.VexRiscv.memory_arbitration_isStuck
|
||||
TOP.VexRiscv.memory_arbitration_isStuckByOthers
|
||||
TOP.VexRiscv.prefetch_arbitration_isStuck
|
||||
TOP.VexRiscv.prefetch_arbitration_isStuckByOthers
|
||||
TOP.VexRiscv.writeBack_arbitration_isStuck
|
||||
TOP.VexRiscv.writeBack_arbitration_isStuckByOthers
|
||||
TOP.VexRiscv.iBus_cmd_valid
|
||||
TOP.VexRiscv.iBus_cmd_ready
|
||||
@22
|
||||
TOP.VexRiscv.iBus_cmd_payload_pc[31:0]
|
||||
@28
|
||||
TOP.VexRiscv.iBus_rsp_error
|
||||
@22
|
||||
TOP.VexRiscv.iBus_rsp_inst[31:0]
|
||||
@28
|
||||
TOP.VexRiscv.iBus_rsp_ready
|
||||
TOP.VexRiscv.debug_bus_cmd_valid
|
||||
@22
|
||||
TOP.VexRiscv.BranchPlugin_counter[8:0]
|
||||
@28
|
||||
TOP.VexRiscv.decode_IS_EBREAK
|
||||
TOP.VexRiscv.execute_IS_EBREAK
|
||||
TOP.VexRiscv.CsrPlugin_pipelineLiberator_done
|
||||
TOP.VexRiscv.CsrPlugin_pipelineLiberator_enable
|
||||
TOP.VexRiscv.DebugPlugin_haltIt
|
||||
@22
|
||||
TOP.VexRiscv.writeBack_INSTRUCTION[31:0]
|
||||
@29
|
||||
TOP.VexRiscv.DebugPlugin_stepIt
|
||||
@22
|
||||
TOP.VexRiscv.debug_bus_cmd_payload_address[7:0]
|
||||
TOP.VexRiscv.debug_bus_cmd_payload_data[31:0]
|
||||
@28
|
||||
TOP.VexRiscv.debug_bus_cmd_payload_wr
|
||||
TOP.VexRiscv.debug_bus_cmd_ready
|
||||
TOP.VexRiscv.debug_bus_cmd_valid
|
||||
@22
|
||||
TOP.VexRiscv.debug_bus_rsp_data[31:0]
|
||||
@28
|
||||
TOP.VexRiscv.debug_resetOut
|
||||
TOP.VexRiscv.debugReset
|
||||
[pattern_trace] 1
|
||||
[pattern_trace] 0
|
||||
|
|
@ -22,7 +22,7 @@ Arr_1_Glob[8]: 7
|
|||
Arr_2_Glob[8][7]: 210
|
||||
should be: Number_Of_Runs + 10
|
||||
Ptr_Glob->
|
||||
Ptr_Comp: 92416
|
||||
Ptr_Comp: -2147458812
|
||||
should be: (implementation-dependent)
|
||||
Discr: 0
|
||||
should be: 0
|
||||
|
|
@ -33,7 +33,7 @@ Ptr_Glob->
|
|||
Str_Comp: DHRYSTONE PROGRAM, SOME STRING
|
||||
should be: DHRYSTONE PROGRAM, SOME STRING
|
||||
Next_Ptr_Glob->
|
||||
Ptr_Comp: 92416
|
||||
Ptr_Comp: -2147458812
|
||||
should be: (implementation-dependent), same as above
|
||||
Discr: 0
|
||||
should be: 0
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -22,7 +22,7 @@ Arr_1_Glob[8]: 7
|
|||
Arr_2_Glob[8][7]: 210
|
||||
should be: Number_Of_Runs + 10
|
||||
Ptr_Glob->
|
||||
Ptr_Comp: 89136
|
||||
Ptr_Comp: -2147459860
|
||||
should be: (implementation-dependent)
|
||||
Discr: 0
|
||||
should be: 0
|
||||
|
|
@ -33,7 +33,7 @@ Ptr_Glob->
|
|||
Str_Comp: DHRYSTONE PROGRAM, SOME STRING
|
||||
should be: DHRYSTONE PROGRAM, SOME STRING
|
||||
Next_Ptr_Glob->
|
||||
Ptr_Comp: 89136
|
||||
Ptr_Comp: -2147459860
|
||||
should be: (implementation-dependent), same as above
|
||||
Discr: 0
|
||||
should be: 0
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -84,6 +84,11 @@ void loadHexImpl(string path,Memory* mem) {
|
|||
if(fp == 0){
|
||||
cout << path << " not found" << endl;
|
||||
}
|
||||
//Preload 0x0 <-> 0x80000000 jumps
|
||||
((uint32_t*)mem->get(0))[0] = 0x800000b7;
|
||||
((uint32_t*)mem->get(0))[1] = 0x000080e7;
|
||||
((uint32_t*)mem->get(0x80000000))[0] = 0x00000097;
|
||||
|
||||
fseek(fp, 0, SEEK_END);
|
||||
uint32_t size = ftell(fp);
|
||||
fseek(fp, 0, SEEK_SET);
|
||||
|
|
@ -1455,7 +1460,7 @@ public:
|
|||
while(resetDone != true){usleep(100);}
|
||||
|
||||
while((readCmd(2,debugAddress) & RISCV_SPINAL_FLAGS_HALT) == 0){usleep(100);}
|
||||
if((readValue = readCmd(2,debugAddress + 4)) != 0x0000000C){
|
||||
if((readValue = readCmd(2,debugAddress + 4)) != 0x8000000C){
|
||||
printf("wrong break PC %x\n",readValue);
|
||||
clientFail = true; return;
|
||||
}
|
||||
|
|
@ -1479,12 +1484,13 @@ public:
|
|||
}
|
||||
|
||||
writeCmd(2, debugAddress + 4, 0x13 + (1 << 7) + (40 << 20)); //Write x1 with 40
|
||||
writeCmd(2, debugAddress + 4, 0x13 + (29 << 7) + (0x10 << 20)); //Write x29 with 0x10
|
||||
writeCmd(2, debugAddress + 4, 0x80000eb7); //Write x29 with 0x10
|
||||
writeCmd(2, debugAddress + 4, 0x010e8e93); //Write x29 with 0x10
|
||||
writeCmd(2, debugAddress + 4, 0x67 + (29 << 15)); //Branch x29
|
||||
writeCmd(2, debugAddress + 0, RISCV_SPINAL_FLAGS_HALT_CLEAR); //Run CPU
|
||||
|
||||
while((readCmd(2,debugAddress) & RISCV_SPINAL_FLAGS_HALT) == 0){usleep(100);}
|
||||
if((readValue = readCmd(2,debugAddress + 4)) != 0x00000014){
|
||||
if((readValue = readCmd(2,debugAddress + 4)) != 0x80000014){
|
||||
printf("wrong break PC 2 %x\n",readValue);
|
||||
clientFail = true; return;
|
||||
}
|
||||
|
|
@ -1496,14 +1502,16 @@ public:
|
|||
clientFail = true; return;
|
||||
}
|
||||
|
||||
writeCmd(2, debugAddress + 4, 0x13 + (29 << 7) + (0x18 << 20)); //Write x29 with 0x10
|
||||
|
||||
writeCmd(2, debugAddress + 4, 0x80000eb7); //Write x29 with 0x10
|
||||
writeCmd(2, debugAddress + 4, 0x018e8e93); //Write x29 with 0x10
|
||||
writeCmd(2, debugAddress + 4, 0x67 + (29 << 15)); //Branch x29
|
||||
writeCmd(2, debugAddress + 0, RISCV_SPINAL_FLAGS_HALT_CLEAR); //Run CPU
|
||||
|
||||
|
||||
|
||||
while((readCmd(2,debugAddress) & RISCV_SPINAL_FLAGS_HALT) == 0){usleep(100);}
|
||||
if((readValue = readCmd(2,debugAddress + 4)) != 0x00000024){
|
||||
if((readValue = readCmd(2,debugAddress + 4)) != 0x80000024){
|
||||
printf("wrong break PC 2 %x\n",readValue);
|
||||
clientFail = true; return;
|
||||
}
|
||||
|
|
@ -1682,7 +1690,7 @@ int main(int argc, char **argv, char **env) {
|
|||
|
||||
#ifdef ISA_TEST
|
||||
|
||||
redo(REDO,TestA().run();)
|
||||
// redo(REDO,TestA().run();)
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
:0200000480007A
|
||||
:100000009300A000130140019301E0017300100070
|
||||
:10001000B381200073001000938111009381A1002F
|
||||
:080020009381410673001000FA
|
||||
:0400000540000000B7
|
||||
:04000005800000284F
|
||||
:00000001FF
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
34
src/test/scala/vexriscv/experimental/Experiments.scala
Normal file
34
src/test/scala/vexriscv/experimental/Experiments.scala
Normal file
|
|
@ -0,0 +1,34 @@
|
|||
package vexriscv.experimental
|
||||
|
||||
import spinal.core._
|
||||
|
||||
class Stageable[T <: Data](val dataType : T) extends HardType[T](dataType) with Nameable{
|
||||
setWeakName(this.getClass.getSimpleName.replace("$",""))
|
||||
}
|
||||
|
||||
trait Stage{
|
||||
def read[T <: Data](stageable : Stageable[T]) : T
|
||||
def write[T <: Data](stageable : Stageable[T], value : T, cond : Bool = null) : Unit
|
||||
|
||||
def haltBySelf : Bool //user settable, stuck the instruction, should only be set by the instruction itself
|
||||
def haltByOthers : Bool //When settable, stuck the instruction, should only be set by something else than the stucked instruction
|
||||
def removeIt : Bool //When settable, unschedule the instruction as if it was never executed (no side effect)
|
||||
def flushAll : Bool //When settable, unschedule instructions in the current stage and all prior ones
|
||||
|
||||
def isValid : Bool //Inform if a instruction is in the current stage
|
||||
def isStuck : Bool //Inform if the instruction is stuck (haltItself || haltByOther)
|
||||
def isStuckByOthers: Bool //Inform if the instruction is stuck by sombody else
|
||||
def isRemoved : Bool //Inform if the instruction is going to be unschedule the current cycle
|
||||
def isFlushed : Bool //Inform if the instruction is flushed (flushAll set in the current or subsequents stages)
|
||||
def isFiring : Bool //Inform if the current instruction will go to the next stage the next cycle (isValid && !isStuck && !removeIt)
|
||||
}
|
||||
|
||||
abstract class UnusedStage extends Stage
|
||||
abstract class AsyncStage extends Stage
|
||||
abstract class CycleStage extends Stage
|
||||
abstract class SyncStage extends Stage
|
||||
abstract class CutStage extends Stage
|
||||
|
||||
abstract class PipelineStd{
|
||||
val prefetch, fetch, decode, execute, memory, writeback = 0
|
||||
}
|
||||
Loading…
Reference in a new issue