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Add PMP test to regression suite

This commit is contained in:
Samuel Lindemer 2020-12-01 18:35:51 +01:00
parent c5023ad973
commit d5b1a8f565
9 changed files with 89 additions and 68 deletions
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5
src/main/scala/vexriscv/plugin/PmpPlugin.scala
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@ -140,13 +140,12 @@ class PmpPlugin(regions : Int, ioRange : UInt => Bool) extends Plugin[VexRiscv]
val privilegeService = pipeline.service(classOf[PrivilegeService])
var pcManagerService = pipeline.service(classOf[JumpService])
// Flush proceeding instructions and replay them after any CSR write.
redoInterface = pcManagerService.createJumpInterface(pipeline.execute, -1)
redoInterface.valid := False
redoInterface.payload := decode.input(PC)
val core = pipeline plug new Area {
// Flush proceeding instructions and replay them after any CSR write.
redoInterface.payload := decode.input(PC)
redoInterface.valid := False
// Instantiate pmpaddr0 ... pmpaddr# CSRs.

72
src/test/cpp/raw/pmp/build/pmp.asm
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@ -4,28 +4,26 @@ build/pmp.elf: file format elf32-littleriscv
Disassembly of section .crt_section:
80000000 <trap-0x4>:
80000000: 0240006f j 80000024 <_start>
80000000 <_start>:
80000000: 00000097 auipc ra,0x0
80000004: 01008093 addi ra,ra,16 # 80000010 <trap>
80000008: 30509073 csrw mtvec,ra
8000000c: 0240006f j 80000030 <test0>
80000004 <trap>:
80000004: 341f1073 csrw mepc,t5
80000008: 30200073 mret
80000010 <trap>:
80000010: 341f1073 csrw mepc,t5
80000014: 30200073 mret
8000000c <to_user>:
8000000c: 00014337 lui t1,0x14
80000010: 30033073 csrc mstatus,t1
80000014: 20000313 li t1,512
80000018: 30032073 csrs mstatus,t1
8000001c: 34109073 csrw mepc,ra
80000020: 30200073 mret
80000024 <_start>:
80000024: 00000097 auipc ra,0x0
80000028: fe008093 addi ra,ra,-32 # 80000004 <trap>
8000002c: 30509073 csrw mtvec,ra
80000018 <to_user>:
80000018: 00014337 lui t1,0x14
8000001c: 30033073 csrc mstatus,t1
80000020: 20000313 li t1,512
80000024: 30032073 csrs mstatus,t1
80000028: 34109073 csrw mepc,ra
8000002c: 30200073 mret
80000030 <test0>:
80000030: 00000e93 li t4,0
80000030: 00000e13 li t3,0
80000034: 00000f17 auipc t5,0x0
80000038: 1f0f0f13 addi t5,t5,496 # 80000224 <fail>
8000003c: 800002b7 lui t0,0x80000
@ -39,15 +37,15 @@ Disassembly of section .crt_section:
8000005c: 000e2383 lw t2,0(t3)
80000060: 1c731263 bne t1,t2,80000224 <fail>
80000064: 071a1f37 lui t5,0x71a1
80000068: 808f0f13 addi t5,t5,-2040 # 71a0808 <trap-0x78e5f7fc>
80000068: 808f0f13 addi t5,t5,-2040 # 71a0808 <_start-0x78e5f7f8>
8000006c: 3a0f1073 csrw pmpcfg0,t5
80000070: 191c0f37 lui t5,0x191c0
80000074: 504f0f13 addi t5,t5,1284 # 191c0504 <trap-0x66e3fb00>
80000074: 504f0f13 addi t5,t5,1284 # 191c0504 <_start-0x66e3fafc>
80000078: 3a1f1073 csrw pmpcfg1,t5
8000007c: 01800f13 li t5,24
80000080: 3a2f1073 csrw pmpcfg2,t5
80000084: 0f1e2f37 lui t5,0xf1e2
80000088: 900f0f13 addi t5,t5,-1792 # f1e1900 <trap-0x70e1e704>
80000088: 900f0f13 addi t5,t5,-1792 # f1e1900 <_start-0x70e1e700>
8000008c: 3a3f1073 csrw pmpcfg3,t5
80000090: 20000f37 lui t5,0x20000
80000094: 3b0f1073 csrw pmpaddr0,t5
@ -56,22 +54,22 @@ Disassembly of section .crt_section:
800000a0: 20002f37 lui t5,0x20002
800000a4: 3b2f1073 csrw pmpaddr2,t5
800000a8: 20004f37 lui t5,0x20004
800000ac: ffff0f13 addi t5,t5,-1 # 20003fff <trap-0x5fffc005>
800000ac: ffff0f13 addi t5,t5,-1 # 20003fff <_start-0x5fffc001>
800000b0: 3b3f1073 csrw pmpaddr3,t5
800000b4: 20004f37 lui t5,0x20004
800000b8: ffff0f13 addi t5,t5,-1 # 20003fff <trap-0x5fffc005>
800000b8: ffff0f13 addi t5,t5,-1 # 20003fff <_start-0x5fffc001>
800000bc: 3b4f1073 csrw pmpaddr4,t5
800000c0: 20004f37 lui t5,0x20004
800000c4: ffff0f13 addi t5,t5,-1 # 20003fff <trap-0x5fffc005>
800000c4: ffff0f13 addi t5,t5,-1 # 20003fff <_start-0x5fffc001>
800000c8: 3b5f1073 csrw pmpaddr5,t5
800000cc: 20002f37 lui t5,0x20002
800000d0: ffff0f13 addi t5,t5,-1 # 20001fff <trap-0x5fffe005>
800000d0: ffff0f13 addi t5,t5,-1 # 20001fff <_start-0x5fffe001>
800000d4: 3b6f1073 csrw pmpaddr6,t5
800000d8: 20004f37 lui t5,0x20004
800000dc: ffff0f13 addi t5,t5,-1 # 20003fff <trap-0x5fffc005>
800000dc: ffff0f13 addi t5,t5,-1 # 20003fff <_start-0x5fffc001>
800000e0: 3b7f1073 csrw pmpaddr7,t5
800000e4: 20004f37 lui t5,0x20004
800000e8: ffff0f13 addi t5,t5,-1 # 20003fff <trap-0x5fffc005>
800000e8: ffff0f13 addi t5,t5,-1 # 20003fff <_start-0x5fffc001>
800000ec: 3b8f1073 csrw pmpaddr8,t5
800000f0: 00000f13 li t5,0
800000f4: 3b9f1073 csrw pmpaddr9,t5
@ -88,7 +86,7 @@ Disassembly of section .crt_section:
80000120: 00000f13 li t5,0
80000124: 3bff1073 csrw pmpaddr15,t5
80000128: 00c10337 lui t1,0xc10
8000012c: fee30313 addi t1,t1,-18 # c0ffee <trap-0x7f3f0016>
8000012c: fee30313 addi t1,t1,-18 # c0ffee <_start-0x7f3f0012>
80000130: 0062a023 sw t1,0(t0)
80000134: 006e2023 sw t1,0(t3)
80000138: 0002a383 lw t2,0(t0)
@ -97,11 +95,11 @@ Disassembly of section .crt_section:
80000144: 0e731063 bne t1,t2,80000224 <fail>
80000148 <test1>:
80000148: 00100e93 li t4,1
80000148: 00100e13 li t3,1
8000014c: 00000f17 auipc t5,0x0
80000150: 0d8f0f13 addi t5,t5,216 # 80000224 <fail>
80000154: 079a1f37 lui t5,0x79a1
80000158: 808f0f13 addi t5,t5,-2040 # 79a0808 <trap-0x7865f7fc>
80000158: 808f0f13 addi t5,t5,-2040 # 79a0808 <_start-0x7865f7f8>
8000015c: 3a0f1073 csrw pmpcfg0,t5
80000160: deadc337 lui t1,0xdeadc
80000164: eef30313 addi t1,t1,-273 # deadbeef <pass+0x5eadbcbf>
@ -112,11 +110,11 @@ Disassembly of section .crt_section:
80000178: 0ac0006f j 80000224 <fail>
8000017c <test2>:
8000017c: 00200e93 li t4,2
8000017c: 00200e13 li t3,2
80000180: 00000f17 auipc t5,0x0
80000184: 0a4f0f13 addi t5,t5,164 # 80000224 <fail>
80000188: 071a1f37 lui t5,0x71a1
8000018c: 808f0f13 addi t5,t5,-2040 # 71a0808 <trap-0x78e5f7fc>
8000018c: 808f0f13 addi t5,t5,-2040 # 71a0808 <_start-0x78e5f7f8>
80000190: 3a0f1073 csrw pmpcfg0,t5
80000194: deadc337 lui t1,0xdeadc
80000198: eef30313 addi t1,t1,-273 # deadbeef <pass+0x5eadbcbf>
@ -127,15 +125,15 @@ Disassembly of section .crt_section:
800001ac: 0780006f j 80000224 <fail>
800001b0 <test3>:
800001b0: 00300e93 li t4,3
800001b0: 00300e13 li t3,3
800001b4: 00000f17 auipc t5,0x0
800001b8: 070f0f13 addi t5,t5,112 # 80000224 <fail>
800001bc: 00000097 auipc ra,0x0
800001c0: 00c08093 addi ra,ra,12 # 800001c8 <test4>
800001c4: e49ff06f j 8000000c <to_user>
800001c4: e55ff06f j 80000018 <to_user>
800001c8 <test4>:
800001c8: 00400e93 li t4,4
800001c8: 00400e13 li t3,4
800001cc: 00000f17 auipc t5,0x0
800001d0: 058f0f13 addi t5,t5,88 # 80000224 <fail>
800001d4: deadc337 lui t1,0xdeadc
@ -147,7 +145,7 @@ Disassembly of section .crt_section:
800001ec: 0380006f j 80000224 <fail>
800001f0 <test5>:
800001f0: 00500e93 li t4,5
800001f0: 00500e13 li t3,5
800001f4: 00000f17 auipc t5,0x0
800001f8: 03cf0f13 addi t5,t5,60 # 80000230 <pass>
800001fc: 80010e37 lui t3,0x80010
@ -164,7 +162,7 @@ Disassembly of section .crt_section:
80000224 <fail>:
80000224: f0100137 lui sp,0xf0100
80000228: f2410113 addi sp,sp,-220 # f00fff24 <pass+0x700ffcf4>
8000022c: 01d12023 sw t4,0(sp)
8000022c: 01c12023 sw t3,0(sp)
80000230 <pass>:
80000230: f0100137 lui sp,0xf0100

BIN
src/test/cpp/raw/pmp/build/pmp.elf
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Binary file not shown.

22
src/test/cpp/raw/pmp/build/pmp.hex
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@ -1,8 +1,8 @@
:0200000480007A
:100000006F00400273101F3473002030374301002B
:1000100073300330130300207320033073901034C7
:100020007300203097000000938000FE73905030E2
:10003000930E0000170F0000130F0F1FB702008070
:100000009700000093800001739050306F00400211
:1000100073101F34730020303743010073300330F6
:1000200013030020732003307390103473002030CA
:10003000130E0000170F0000130F0F1FB7020080F0
:10004000378E008037C3ADDE1303F3EE23A06200CA
:1000500023206E0083A302006316731C83230E000B
:100060006312731C371F1A07130F8F8073100F3A18
@ -19,21 +19,21 @@
:10011000130F00007310DF3B130F00007310EF3B51
:10012000130F00007310FF3B3703C1001303E3FEFE
:1001300023A0620023206E0083A302006314730EC9
:1001400083230E006310730E930E1000170F000030
:1001400083230E006310730E130E1000170F0000B0
:10015000130F8F0D371F9A07130F8F8073100F3AED
:1001600037C3ADDE1303F3EE23206E00170F00003C
:10017000130F0F0183230E006F00C00A930E20009F
:10017000130F0F0183230E006F00C00A130E20001F
:10018000170F0000130F4F0A371F1A07130F8F8026
:1001900073100F3A37C3ADDE1303F3EE23206E0066
:1001A000170F0000130F0F0183230E006F0080074D
:1001B000930E3000170F0000130F0F079700000079
:1001C0009380C0006FF09FE4930E4000170F000073
:1001B000130E3000170F0000130F0F0797000000F9
:1001C0009380C0006FF05FE5130E4000170F000032
:1001D000130F8F0537C3ADDE1303F3EE23206E003C
:1001E000170F0000130F0F0183230E006F00800311
:1001F000930E5000170F0000130FCF03370E01802E
:1001F000130E5000170F0000130FCF03370E0180AE
:1002000037C3ADDE1303F3EE23A0620083A3020025
:10021000631A730083230E00170F0000130F8F0162
:1002200023207E00370110F0130141F22320D10179
:1002200023207E00370110F0130141F22320C10189
:0C023000370110F0130101F2232001003F
:040000058000002453
:040000058000000077
:00000001FF

5
src/test/cpp/raw/pmp/build/pmp.map
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@ -19,8 +19,9 @@ LOAD /opt/riscv/lib/gcc/riscv64-unknown-elf/10.2.0/libgcc.a
0x0000000080000000 . = ALIGN (0x4)
*crt.o(.text)
.text 0x0000000080000000 0x23c build/src/crt.o
0x0000000080000004 trap
0x0000000080000024 _start
0x0000000080000000 _start
0x0000000080000010 trap
0x0000000080000018 to_user
OUTPUT(build/pmp.elf elf32-littleriscv)
.data 0x000000008000023c 0x0

21
src/test/cpp/raw/pmp/src/crt.S
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@ -1,4 +1,10 @@
#define TEST_ID x29
/*
* Copyright (c) 2020 Samuel Lindemer <samuel.lindemer@ri.se>
*
* SPDX-License-Identifier: MIT
*/
#define TEST_ID x28
#define TRAP_RA x30
#define PMPCFG0 0x071a0808
@ -24,15 +30,18 @@
#define PMPADDR14 0x00000000 // NAPOT WX
#define PMPADDR15 0x00000000 // TOR RWX
.global trap
.global _start
_start:
la x1, trap
csrw mtvec, x1
j test0
j _start
.global trap
trap:
csrw mepc, TRAP_RA
mret
.global to_user
to_user:
li t1, 0x14000
csrc mstatus, t1
@ -41,10 +50,6 @@ to_user:
csrw mepc, ra
mret
_start:
la x1, trap
csrw mtvec, x1
// configure PMP, attempt read/write from machine mode
test0:
li TEST_ID, 0

2
src/test/cpp/regression/main.cpp
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@ -3871,7 +3871,7 @@ int main(int argc, char **argv, char **env) {
#endif
#ifdef PMP
redo(REDO,WorkspaceRegression("pmp").withRiscvRef()->loadHex(string(REGRESSION_PATH) + "../raw/lrsc/build/pmp.hex")->bootAt(0x00000000u)->run(10e3););
redo(REDO,WorkspaceRegression("pmp").withRiscvRef()->loadHex(string(REGRESSION_PATH) + "../raw/pmp/build/pmp.hex")->bootAt(0x00000000u)->run(10e3););
#endif
#ifdef AMO

5
src/test/cpp/regression/makefile
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@ -15,6 +15,7 @@ CSR_SKIP_TEST?=no
EBREAK?=no
FENCEI?=no
MMU?=yes
PMP?=yes
SEED?=no
LRSC?=no
AMO?=no
@ -217,6 +218,10 @@ ifeq ($(MMU),yes)
ADDCFLAGS += -CFLAGS -DMMU
endif
ifeq ($(PMP),yes)
ADDCFLAGS += -CFLAGS -DPMP
endif
ifeq ($(MUL),yes)
ADDCFLAGS += -CFLAGS -DMUL
endif

25
src/test/scala/vexriscv/TestIndividualFeatures.scala
View File

@ -48,6 +48,7 @@ class VexRiscvUniverse extends ConfigUniverse
object VexRiscvUniverse{
val CATCH_ALL = new VexRiscvUniverse
val MMU = new VexRiscvUniverse
val PMP = new VexRiscvUniverse
val FORCE_MULDIV = new VexRiscvUniverse
val SUPERVISOR = new VexRiscvUniverse
val NO_WRITEBACK = new VexRiscvUniverse
@ -468,12 +469,12 @@ class DBusDimension extends VexRiscvDimension("DBus") {
}
class MmuDimension extends VexRiscvDimension("DBus") {
class MmuPmpDimension extends VexRiscvDimension("DBus") {
override def randomPositionImpl(universes: Seq[ConfigUniverse], r: Random) = {
if(universes.contains(VexRiscvUniverse.MMU)) {
new VexRiscvPosition("WithMmu") {
override def testParam = "MMU=yes"
override def testParam = "MMU=yes PMP=no"
override def applyOn(config: VexRiscvConfig): Unit = {
config.plugins += new MmuPlugin(
@ -481,9 +482,20 @@ class MmuDimension extends VexRiscvDimension("DBus") {
)
}
}
} else if (universes.contains(VexRiscvUniverse.PMP)) {
new VexRiscvPosition("WithPmp") {
override def testParam = "MMU=no PMP=yes"
override def applyOn(config: VexRiscvConfig): Unit = {
config.plugins += new PmpPlugin(
regions = 16,
ioRange = _ (31 downto 28) === 0xF
)
}
}
} else {
new VexRiscvPosition("NoMmu") {
override def testParam = "MMU=no"
new VexRiscvPosition("NoMemProtect") {
override def testParam = "MMU=no PMP=no"
override def applyOn(config: VexRiscvConfig): Unit = {
config.plugins += new StaticMemoryTranslatorPlugin(
@ -661,7 +673,7 @@ class TestIndividualFeatures extends MultithreadedFunSuite {
new CsrDimension(/*sys.env.getOrElse("VEXRISCV_REGRESSION_FREERTOS_COUNT", "1")*/ "0", zephyrCount, linuxRegression), //Freertos old port software is broken
new DecoderDimension,
new DebugDimension,
new MmuDimension
new MmuPmpDimension
)
var clockCounter = 0l
@ -749,6 +761,7 @@ class TestIndividualFeatures extends MultithreadedFunSuite {
} else {
if(machineOsRate > rand.nextDouble()) {
universe += VexRiscvUniverse.CATCH_ALL
universe += VexRiscvUniverse.PMP
if(demwRate < rand.nextDouble()){
universe += VexRiscvUniverse.NO_WRITEBACK
}
@ -776,4 +789,4 @@ class TestIndividualFeatures extends MultithreadedFunSuite {
val clockPerSecond = (clockCounter/time*1e-3).toLong
println(s"Duration=${(time/60).toInt}mn clocks=${(clockCounter*1e-6).toLong}M clockPerSecond=${clockPerSecond}K")
}
}
}