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VexRiscv
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remove interrupt assertion

This commit is contained in:
Charles Papon 2019-04-21 19:45:24 +02:00
parent 0e10c460c3
commit d7ca153c8b
1 changed files with 2 additions and 15 deletions
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17
src/test/cpp/regression/main.cpp
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@ -498,13 +498,6 @@ public:
switch(targetPrivilege){
case 3:
if(interrupt){
if(!status.mie || !(ie.raw & (1 << cause)) || !(getIp().raw & (1 << cause))){
cout << "DUT had trigger an interrupts which isnt pending in REF" << endl;
fail();
}
}
if(valueWrite) mbadaddr = value;
mcause.interrupt = interrupt;
mcause.exceptionCode = cause;
@ -514,12 +507,6 @@ public:
mepc = pc;
break;
case 1:
if(interrupt){
if(!status.sie || !(ie.raw & (1 << cause)) || !(getIp().raw & (1 << cause))){
cout << "DUT had trigger an interrupts which isnt pending in REF" << endl;
fail();
}
}
if(valueWrite) sbadaddr = value;
scause.interrupt = interrupt;
scause.exceptionCode = cause;
@ -3370,8 +3357,8 @@ string zephyrTests[] = {
"tests_kernel_fifo_fifo_api",
"tests_kernel_mbox_mbox_usage",
// "tests_kernel_mem_pool_mem_pool_threadsafe", //Too long
"tests_kernel_sleep",
"tests_kernel_timer_timer_api"
"tests_kernel_sleep"
// "tests_kernel_timer_timer_api" //Lock like if the CPU is too slow, it will make it fail
};