move to SpinalHDL 1.1.7, add more default value for plugins parameters

build.sbt

@@ -9,8 +9,8 @@ scalaVersion := "2.11.6"
 EclipseKeys.withSource := true
 
 libraryDependencies ++= Seq(
-  "com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.1.6",
+  "com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.1.7",
-  "com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.1.6",
+  "com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.1.7",
   "org.scalatest" % "scalatest_2.11" % "2.2.1",
   "org.yaml" % "snakeyaml" % "1.8"
 )

src/main/scala/vexriscv/VexRiscv.scala

@@ -6,7 +6,7 @@ import spinal.core._
 import scala.collection.mutable.ArrayBuffer
 
 object VexRiscvConfig{
-  def apply(plugins : Seq[Plugin[VexRiscv]]) : VexRiscvConfig = {
+  def apply(plugins : Seq[Plugin[VexRiscv]] = ArrayBuffer()) : VexRiscvConfig = {
     val config = VexRiscvConfig()
     config.plugins ++= plugins
     config

src/main/scala/vexriscv/demo/SynthesisBench.scala

@@ -101,17 +101,17 @@ object VexRiscvSynthesisBench {
     }
 
 
-//    val rtls = List(smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache, fullNoMmuNoCache, noCacheNoMmuMaxPerf, fullNoMmuMaxPerf, fullNoMmu, full)
+    val rtls = List(smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache, fullNoMmuNoCache, noCacheNoMmuMaxPerf, fullNoMmuMaxPerf, fullNoMmu, full)
-val rtls = List(smallestNoCsr)
+//val rtls = List(smallestNoCsr)
     //      val rtls = List(smallAndProductive, smallAndProductiveWithICache, fullNoMmuMaxPerf, fullNoMmu, full)
 //    val rtls = List(smallAndProductive,  full)
 
-    val targets = /*XilinxStdTargets(
+    val targets = XilinxStdTargets(
       vivadoArtix7Path = "/eda/Xilinx/Vivado/2017.2/bin"
     ) ++ AlteraStdTargets(
       quartusCycloneIVPath = "/eda/intelFPGA_lite/17.0/quartus/bin",
       quartusCycloneVPath  = "/eda/intelFPGA_lite/17.0/quartus/bin"
-    ) ++  */IcestormStdTargets()
+    ) ++  IcestormStdTargets()
 
 //    val targets = IcestormStdTargets()
     Bench(rtls, targets, "/eda/tmp/")

src/main/scala/vexriscv/plugin/BranchPlugin.scala

@@ -49,7 +49,7 @@ trait PredictionInterface{
 }
 
 class BranchPlugin(earlyBranch : Boolean,
-                   catchAddressMisaligned : Boolean) extends Plugin[VexRiscv] with PredictionInterface{
+                   catchAddressMisaligned : Boolean = false) extends Plugin[VexRiscv] with PredictionInterface{
 
 
   lazy val branchStage = if(earlyBranch) pipeline.execute else pipeline.memory

src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala

@@ -182,7 +182,7 @@ case class DBusSimpleBus() extends Bundle with IMasterSlave{
 }
 
 
-class DBusSimplePlugin(catchAddressMisaligned : Boolean, catchAccessFault : Boolean, earlyInjection : Boolean = false) extends Plugin[VexRiscv]{
+class DBusSimplePlugin(catchAddressMisaligned : Boolean = false, catchAccessFault : Boolean = false, earlyInjection : Boolean = false) extends Plugin[VexRiscv]{
 
   var dBus  : DBusSimpleBus = null
 

src/main/scala/vexriscv/plugin/DecoderSimplePlugin.scala

@@ -44,7 +44,7 @@ case class Masked(value : BigInt,care : BigInt){
   def toString(bitCount : Int) = (0 until bitCount).map(i => if(care.testBit(i)) (if(value.testBit(i)) "1" else "0") else "-").reverseIterator.reduce(_+_)
 }
 
-class DecoderSimplePlugin(catchIllegalInstruction : Boolean, forceLegalInstructionComputation : Boolean = false) extends Plugin[VexRiscv] with DecoderService {
+class DecoderSimplePlugin(catchIllegalInstruction : Boolean = false, forceLegalInstructionComputation : Boolean = false) extends Plugin[VexRiscv] with DecoderService {
   override def add(encoding: Seq[(MaskedLiteral, Seq[(Stageable[_ <: BaseType], Any)])]): Unit = encoding.foreach(e => this.add(e._1,e._2))
   override def add(key: MaskedLiteral, values: Seq[(Stageable[_ <: BaseType], Any)]): Unit = {
     val instructionModel = encodings.getOrElseUpdate(key,ArrayBuffer[(Stageable[_ <: BaseType], BaseType)]())

src/main/scala/vexriscv/plugin/HazardSimplePlugin.scala

@@ -5,10 +5,10 @@ import spinal.core._
 import spinal.lib._
 
 
-class HazardSimplePlugin(bypassExecute : Boolean,
+class HazardSimplePlugin(bypassExecute : Boolean = false,
-                         bypassMemory: Boolean,
+                         bypassMemory: Boolean = false,
-                         bypassWriteBack: Boolean,
+                         bypassWriteBack: Boolean = false,
-                         bypassWriteBackBuffer : Boolean,
+                         bypassWriteBackBuffer : Boolean = false,
                          pessimisticUseSrc : Boolean = false,
                          pessimisticWriteRegFile : Boolean = false,
                          pessimisticAddressMatch : Boolean = false) extends Plugin[VexRiscv] {

src/main/scala/vexriscv/plugin/MemoryTranslatorPlugin.scala

@@ -64,7 +64,7 @@ class MemoryTranslatorPlugin(tlbSize : Int,
       val shared = new Area {
         val cache = Mem(CacheLine(), tlbSize)
         var free = True
-        val readAddr = cache.addressType.assignDontCare()
+        val readAddr = cache.addressType().assignDontCare()
         val readData = RegNext(cache.readSync(readAddr))
       }
 

src/main/scala/vexriscv/plugin/Misc.scala

@@ -126,7 +126,7 @@ object StreamVexPimper{
       val ret = cloneOf(pimped)
 
       val rValid = RegInit(False)
-      val rData = Reg(pimped.dataType)
+      val rData = Reg(pimped.payloadType)
       if(!discardInput) rValid.clearWhen(flush)
 
       pimped.ready := (Bool(collapsBubble) && !ret.valid) || ret.ready
@@ -148,7 +148,7 @@ object StreamVexPimper{
       val ret = cloneOf(pimped)
 
       val rValid = RegInit(False)
-      val rBits = Reg(pimped.dataType)
+      val rBits = Reg(pimped.payloadType)
 
       ret.valid := pimped.valid || rValid
       pimped.ready := !rValid

src/main/scala/vexriscv/plugin/MulDivIterativePlugin.scala

@@ -4,7 +4,7 @@ import spinal.core._
 import spinal.lib._
 import vexriscv.{VexRiscv, _}
 
-class MulDivIterativePlugin(genMul : Boolean, genDiv : Boolean, mulUnrollFactor : Int, divUnrollFactor : Int) extends Plugin[VexRiscv]{
+class MulDivIterativePlugin(genMul : Boolean = true, genDiv : Boolean = true, mulUnrollFactor : Int = 1, divUnrollFactor : Int = 1) extends Plugin[VexRiscv]{
   object IS_MUL extends Stageable(Bool)
   object IS_DIV extends Stageable(Bool)
   object IS_REM extends Stageable(Bool)

src/main/scala/vexriscv/plugin/SrcPlugin.scala

@@ -4,7 +4,7 @@ import vexriscv.{RVC_GEN, Riscv, VexRiscv}
 import spinal.core._
 
 
-class SrcPlugin(separatedAddSub : Boolean, executeInsertion : Boolean = false) extends Plugin[VexRiscv]{
+class SrcPlugin(separatedAddSub : Boolean = false, executeInsertion : Boolean = false) extends Plugin[VexRiscv]{
   override def build(pipeline: VexRiscv): Unit = {
     import pipeline._
     import pipeline.config._

src/test/scala/vexriscv/MuraxSim.scala

@@ -22,7 +22,7 @@ object MuraxSim {
 //    def config = MuraxConfig.default.copy(onChipRamSize = 256 kB)
     def config = MuraxConfig.default.copy(onChipRamSize = 4 kB, onChipRamHexFile = "src/main/ressource/hex/muraxDemo.hex")
 
-    SimConfig.allOptimisation.compile(new Murax(config)).doSimUntilVoid{dut =>
+    SimConfig.allOptimisation.withWave.compile(new Murax(config)).doSimUntilVoid{dut =>
       val mainClkPeriod = (1e12/dut.config.coreFrequency.toDouble).toLong
       val jtagClkPeriod = mainClkPeriod*4
       val uartBaudRate = 115200

src/test/scala/vexriscv/experimental/config.scala

@@ -0,0 +1,36 @@
+package vexriscv.experimental
+
+import spinal.core.SpinalVerilog
+import vexriscv.ip.InstructionCacheConfig
+import vexriscv.{VexRiscv, VexRiscvConfig, plugin}
+import vexriscv.plugin._
+
+import scala.collection.mutable.ArrayBuffer
+
+object Presentation extends App{
+
+  val config = VexRiscvConfig()
+
+  config.plugins ++= List(
+    new IBusSimplePlugin(resetVector = 0x80000000l),
+    new DBusSimplePlugin,
+    new CsrPlugin(CsrPluginConfig.smallest),
+    new DecoderSimplePlugin,
+    new RegFilePlugin(regFileReadyKind = plugin.SYNC),
+    new IntAluPlugin,
+    new SrcPlugin,
+    new MulDivIterativePlugin(
+      mulUnrollFactor = 4,
+      divUnrollFactor = 1
+    ),
+    new FullBarrelShifterPlugin,
+    new HazardSimplePlugin,
+    new BranchPlugin(
+      earlyBranch = false
+    ),
+    new YamlPlugin("cpu0.yaml")
+  )
+
+  new VexRiscv(config)
+}
+