More SMP tests (barrier via AMO and LRSC)
This commit is contained in:
Dolu1990
parent
fd52f9ba50
commit
d88d04dbc4
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@ -10,6 +10,8 @@ import vexriscv.ip.{DataCacheAck, DataCacheConfig, DataCacheMemBus, InstructionC
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import vexriscv.plugin.{BranchPlugin, CsrPlugin, CsrPluginConfig, DBusCachedPlugin, DBusSimplePlugin, DebugPlugin, DecoderSimplePlugin, FullBarrelShifterPlugin, HazardSimplePlugin, IBusCachedPlugin, IBusSimplePlugin, IntAluPlugin, MmuPlugin, MmuPortConfig, MulDivIterativePlugin, MulPlugin, RegFilePlugin, STATIC, SrcPlugin, YamlPlugin}
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import vexriscv.{VexRiscv, VexRiscvConfig, plugin}
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import scala.collection.mutable
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case class VexRiscvSmpClusterParameter( cpuConfigs : Seq[VexRiscvConfig])
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@ -27,7 +29,8 @@ case class VexRiscvSmpCluster(p : VexRiscvSmpClusterParameter,
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val io = new Bundle {
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val dMem = master(Bmb(dMemParameter))
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val iMem = master(Bmb(iMemParameter))
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// val iMem = master(Bmb(iMemParameter))
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val iMems = Vec(master(Bmb(iMemParameter)), p.cpuConfigs.size)
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val timerInterrupts = in Bits(p.cpuConfigs.size bits)
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val externalInterrupts = in Bits(p.cpuConfigs.size bits)
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val externalSupervisorInterrupts = in Bits(p.cpuConfigs.size bits)
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@ -87,18 +90,19 @@ case class VexRiscvSmpCluster(p : VexRiscvSmpClusterParameter,
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io.dMem << invalidateMonitor.io.output
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val iBusArbiter = BmbArbiter(
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p = iBusArbiterParameter,
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portCount = cpus.size,
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pendingRspMax = 64,
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lowerFirstPriority = false,
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inputsWithInv = cpus.map(_ => true),
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inputsWithSync = cpus.map(_ => true),
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pendingInvMax = 16
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)
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(iBusArbiter.io.inputs, cpus).zipped.foreach(_ << _.iBus)
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io.iMem << iBusArbiter.io.output
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// val iBusArbiter = BmbArbiter(
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// p = iBusArbiterParameter,
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// portCount = cpus.size,
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// pendingRspMax = 64,
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// lowerFirstPriority = false,
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// inputsWithInv = cpus.map(_ => true),
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// inputsWithSync = cpus.map(_ => true),
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// pendingInvMax = 16
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// )
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//
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// (iBusArbiter.io.inputs, cpus).zipped.foreach(_ << _.iBus)
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// io.iMem << iBusArbiter.io.output
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(io.iMems, cpus).zipped.foreach(_ << _.iBus)
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}
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@ -274,6 +278,14 @@ object VexRiscvSmpClusterGen {
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}
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object SmpTest{
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val REPORT_OFFSET = 0xF8000000
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val REPORT_THREAD_ID = 0x00
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val REPORT_THREAD_COUNT = 0x04
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val REPORT_END = 0x08
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val REPORT_BARRIER_START = 0x0C
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val REPORT_BARRIER_END = 0x10
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}
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object VexRiscvSmpClusterTest extends App{
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import spinal.core.sim._
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@ -282,21 +294,57 @@ object VexRiscvSmpClusterTest extends App{
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simConfig.allOptimisation
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simConfig.addSimulatorFlag("--threads 1")
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simConfig.compile(VexRiscvSmpClusterGen.vexRiscvCluster()).doSim(seed = 42){dut =>
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simConfig.compile(VexRiscvSmpClusterGen.vexRiscvCluster()).doSimUntilVoid(seed = 42){dut =>
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SimTimeout(10000*10)
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dut.clockDomain.forkSimSpeedPrinter(1.0)
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dut.clockDomain.forkStimulus(10)
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dut.debugClockDomain.forkStimulus(10)
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val hartCount = dut.cpus.size
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JtagTcp(dut.io.jtag, 100)
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val ram = new BmbMemoryAgent(0x100000000l)
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ram.addPort(dut.io.iMem,0,dut.clockDomain,true)
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ram.addPort(dut.io.dMem,0,dut.clockDomain,true)
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val withStall = false
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val cpuEnd = Array.fill(dut.p.cpuConfigs.size)(false)
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val barriers = mutable.HashMap[Int, Int]()
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val ram = new BmbMemoryAgent(0x100000000l){
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var writeData = 0
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override def setByte(address: Long, value: Byte): Unit = {
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if((address & 0xF0000000l) != 0xF0000000l) return super.setByte(address, value)
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val byteId = address & 3
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val mask = 0xFF << (byteId*8)
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writeData = (writeData & ~mask) | ((value.toInt << (byteId*8)) & mask)
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if(byteId != 3) return
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val offset = (address & ~0xF0000000l)-3
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println(s"W[0x${offset.toHexString}] = $writeData")
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offset match {
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case _ if offset >= 0x8000000 && offset < 0x9000000 => {
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val hart = ((offset & 0xFF0000) >> 16).toInt
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val code = (offset & 0x00FFFF).toInt
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val data = writeData
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import SmpTest._
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code match {
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case REPORT_THREAD_ID => assert(data == hart)
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case REPORT_THREAD_COUNT => assert(data == hartCount)
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case REPORT_END => assert(data == 0); assert(cpuEnd(hart) == false); cpuEnd(hart) = true; if(!cpuEnd.exists(_ == false)) simSuccess()
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case REPORT_BARRIER_START => {
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val counter = barriers.getOrElse(data, 0)
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assert(counter < hartCount)
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barriers(data) = counter + 1
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}
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case REPORT_BARRIER_END => {
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val counter = barriers.getOrElse(data, 0)
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assert(counter == hartCount)
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}
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}
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}
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}
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}
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}
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dut.io.iMems.foreach(ram.addPort(_,0,dut.clockDomain,true, withStall)) //Moarr powaaaaa
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// ram.addPort(dut.io.iMem,0,dut.clockDomain,true, withStall)
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ram.addPort(dut.io.dMem,0,dut.clockDomain,true, withStall)
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ram.memory.loadBin(0x80000000l, "src/test/cpp/raw/smp/build/smp.bin")
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sleep(10000*10)
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simSuccess()
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}
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}
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@ -5,104 +5,171 @@ build/smp.elf: file format elf32-littleriscv
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Disassembly of section .crt_section:
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80000000 <_start>:
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80000000: f1402a73 csrr s4,mhartid
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80000004: 00000517 auipc a0,0x0
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80000008: 07850513 addi a0,a0,120 # 8000007c <test1_data>
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8000000c: 00000513 li a0,0
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80000010: 00a52023 sw a0,0(a0)
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80000000: f1402473 csrr s0,mhartid
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80000004: f80002b7 lui t0,0xf8000
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80000008: f1402373 csrr t1,mhartid
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8000000c: 01031313 slli t1,t1,0x10
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80000010: 006282b3 add t0,t0,t1
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80000014: 0082a023 sw s0,0(t0) # f8000000 <barrier_lrsc_value+0x77fffe14>
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80000014 <count_thread_start>:
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80000014: 00100513 li a0,1
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80000018: 00000597 auipc a1,0x0
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8000001c: 05c58593 addi a1,a1,92 # 80000074 <thread_count>
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80000020: 00a5a02f amoadd.w zero,a0,(a1)
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80000018 <count_thread_start>:
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80000018: 00100513 li a0,1
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8000001c: 00000597 auipc a1,0x0
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80000020: 1c458593 addi a1,a1,452 # 800001e0 <thread_count>
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80000024: 00a5a02f amoadd.w zero,a0,(a1)
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80000024 <count_thread_wait>:
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80000024: 00000417 auipc s0,0x0
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80000028: 05042403 lw s0,80(s0) # 80000074 <thread_count>
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8000002c: 0c800513 li a0,200
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80000030: 038000ef jal ra,80000068 <sleep>
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80000034: 00000497 auipc s1,0x0
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80000038: 0404a483 lw s1,64(s1) # 80000074 <thread_count>
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8000003c: fe8494e3 bne s1,s0,80000024 <count_thread_wait>
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80000040: 00000513 li a0,0
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80000044: 00952023 sw s1,0(a0)
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80000048: 0040006f j 8000004c <success>
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80000028 <count_thread_wait>:
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80000028: 00000417 auipc s0,0x0
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8000002c: 1b842403 lw s0,440(s0) # 800001e0 <thread_count>
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80000030: 0c800513 li a0,200
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80000034: 1a0000ef jal ra,800001d4 <sleep>
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80000038: 00000497 auipc s1,0x0
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8000003c: 1a84a483 lw s1,424(s1) # 800001e0 <thread_count>
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80000040: fe8494e3 bne s1,s0,80000028 <count_thread_wait>
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80000044: f80002b7 lui t0,0xf8000
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80000048: 00428293 addi t0,t0,4 # f8000004 <barrier_lrsc_value+0x77fffe18>
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8000004c: f1402373 csrr t1,mhartid
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80000050: 01031313 slli t1,t1,0x10
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80000054: 006282b3 add t0,t0,t1
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80000058: 0092a023 sw s1,0(t0)
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8000004c <success>:
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8000004c: 00800513 li a0,8
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80000050: 00052023 sw zero,0(a0)
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80000054: 0100006f j 80000064 <end>
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8000005c <barrier_amo_test>:
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8000005c: 00100513 li a0,1
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80000060: 040000ef jal ra,800000a0 <barrier_amo>
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80000064: 00200513 li a0,2
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80000068: 038000ef jal ra,800000a0 <barrier_amo>
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8000006c: 00300513 li a0,3
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80000070: 030000ef jal ra,800000a0 <barrier_amo>
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80000074: 00400513 li a0,4
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80000078: 09c000ef jal ra,80000114 <barrier_lrsc>
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8000007c: 00500513 li a0,5
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80000080: 094000ef jal ra,80000114 <barrier_lrsc>
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80000084: 00600513 li a0,6
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80000088: 08c000ef jal ra,80000114 <barrier_lrsc>
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8000008c: 00700513 li a0,7
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80000090: 010000ef jal ra,800000a0 <barrier_amo>
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80000094: 00800513 li a0,8
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80000098: 07c000ef jal ra,80000114 <barrier_lrsc>
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8000009c: 0f40006f j 80000190 <success>
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80000058 <failure>:
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80000058: 00c00513 li a0,12
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8000005c: 00052023 sw zero,0(a0)
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80000060: 0040006f j 80000064 <end>
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800000a0 <barrier_amo>:
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800000a0: f80002b7 lui t0,0xf8000
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800000a4: 00c28293 addi t0,t0,12 # f800000c <barrier_lrsc_value+0x77fffe20>
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800000a8: f1402373 csrr t1,mhartid
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800000ac: 01031313 slli t1,t1,0x10
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800000b0: 006282b3 add t0,t0,t1
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800000b4: 00a2a023 sw a0,0(t0)
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800000b8: 00000297 auipc t0,0x0
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800000bc: 13028293 addi t0,t0,304 # 800001e8 <barrier_amo_value>
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800000c0: 00100313 li t1,1
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800000c4: 0062a02f amoadd.w zero,t1,(t0)
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800000c8: 00000317 auipc t1,0x0
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800000cc: 11832303 lw t1,280(t1) # 800001e0 <thread_count>
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80000064 <end>:
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80000064: 0000006f j 80000064 <end>
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800000d0 <barrier_amo_wait>:
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800000d0: 0002a383 lw t2,0(t0)
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800000d4: fe639ee3 bne t2,t1,800000d0 <barrier_amo_wait>
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800000d8: f80002b7 lui t0,0xf8000
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800000dc: 01028293 addi t0,t0,16 # f8000010 <barrier_lrsc_value+0x77fffe24>
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800000e0: f1402373 csrr t1,mhartid
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800000e4: 01031313 slli t1,t1,0x10
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800000e8: 006282b3 add t0,t0,t1
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800000ec: 00a2a023 sw a0,0(t0)
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80000068 <sleep>:
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80000068: fff50513 addi a0,a0,-1
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8000006c: fe051ee3 bnez a0,80000068 <sleep>
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80000070: 00008067 ret
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800000f0 <barrier_amo_reset>:
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800000f0: f14022f3 csrr t0,mhartid
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800000f4: 00029863 bnez t0,80000104 <barrier_amo_reset_wait>
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800000f8: 00000297 auipc t0,0x0
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800000fc: 0e02a823 sw zero,240(t0) # 800001e8 <barrier_amo_value>
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80000100: 00008067 ret
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80000074 <thread_count>:
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80000074: 0000 unimp
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80000104 <barrier_amo_reset_wait>:
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80000104: 00000297 auipc t0,0x0
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80000108: 0e42a283 lw t0,228(t0) # 800001e8 <barrier_amo_value>
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8000010c: fe029ce3 bnez t0,80000104 <barrier_amo_reset_wait>
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80000110: 00008067 ret
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80000114 <barrier_lrsc>:
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80000114: f80002b7 lui t0,0xf8000
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80000118: 00c28293 addi t0,t0,12 # f800000c <barrier_lrsc_value+0x77fffe20>
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8000011c: f1402373 csrr t1,mhartid
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80000120: 01031313 slli t1,t1,0x10
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80000124: 006282b3 add t0,t0,t1
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80000128: 00a2a023 sw a0,0(t0)
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8000012c: 00000297 auipc t0,0x0
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80000130: 0c028293 addi t0,t0,192 # 800001ec <barrier_lrsc_value>
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80000134 <barrier_lrsc_try>:
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80000134: 1002a32f lr.w t1,(t0)
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80000138: 00130313 addi t1,t1,1
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8000013c: 1862a32f sc.w t1,t1,(t0)
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80000140: fe031ae3 bnez t1,80000134 <barrier_lrsc_try>
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80000144: 00000317 auipc t1,0x0
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80000148: 09c32303 lw t1,156(t1) # 800001e0 <thread_count>
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8000014c <barrier_lrsc_wait>:
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8000014c: 0002a383 lw t2,0(t0)
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80000150: fe639ee3 bne t2,t1,8000014c <barrier_lrsc_wait>
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80000154: f80002b7 lui t0,0xf8000
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80000158: 01028293 addi t0,t0,16 # f8000010 <barrier_lrsc_value+0x77fffe24>
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8000015c: f1402373 csrr t1,mhartid
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80000160: 01031313 slli t1,t1,0x10
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80000164: 006282b3 add t0,t0,t1
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80000168: 00a2a023 sw a0,0(t0)
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8000016c <barrier_lrsc_reset>:
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8000016c: f14022f3 csrr t0,mhartid
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80000170: 00029863 bnez t0,80000180 <barrier_lrsc_reset_wait>
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80000174: 00000297 auipc t0,0x0
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80000178: 0602ac23 sw zero,120(t0) # 800001ec <barrier_lrsc_value>
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8000017c: 00008067 ret
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80000180 <barrier_lrsc_reset_wait>:
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80000180: 00000297 auipc t0,0x0
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80000184: 06c2a283 lw t0,108(t0) # 800001ec <barrier_lrsc_value>
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80000188: fe029ce3 bnez t0,80000180 <barrier_lrsc_reset_wait>
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8000018c: 00008067 ret
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80000190 <success>:
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80000190: 00000413 li s0,0
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80000194: f80002b7 lui t0,0xf8000
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80000198: 00828293 addi t0,t0,8 # f8000008 <barrier_lrsc_value+0x77fffe1c>
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8000019c: f1402373 csrr t1,mhartid
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800001a0: 01031313 slli t1,t1,0x10
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800001a4: 006282b3 add t0,t0,t1
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800001a8: 0082a023 sw s0,0(t0)
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800001ac: 0240006f j 800001d0 <end>
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800001b0 <failure>:
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800001b0: 00100413 li s0,1
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800001b4: f80002b7 lui t0,0xf8000
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800001b8: 00828293 addi t0,t0,8 # f8000008 <barrier_lrsc_value+0x77fffe1c>
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800001bc: f1402373 csrr t1,mhartid
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800001c0: 01031313 slli t1,t1,0x10
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800001c4: 006282b3 add t0,t0,t1
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800001c8: 0082a023 sw s0,0(t0)
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800001cc: 0040006f j 800001d0 <end>
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800001d0 <end>:
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800001d0: 0000006f j 800001d0 <end>
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800001d4 <sleep>:
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800001d4: fff50513 addi a0,a0,-1
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800001d8: fe051ee3 bnez a0,800001d4 <sleep>
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800001dc: 00008067 ret
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800001e0 <thread_count>:
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800001e0: 0000 unimp
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...
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80000078 <shared_memory_1>:
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80000078: 0000 unimp
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800001e4 <shared_memory_1>:
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800001e4: 0000 unimp
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...
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8000007c <test1_data>:
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8000007c: 0000000b 0xb
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80000080 <test2_data>:
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80000080: 0016 c.slli zero,0x5
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800001e8 <barrier_amo_value>:
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800001e8: 0000 unimp
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...
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80000084 <test3_data>:
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80000084: 0049 c.nop 18
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800001ec <barrier_lrsc_value>:
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800001ec: 0000 unimp
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...
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80000088 <test4_data>:
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80000088: 003a c.slli zero,0xe
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...
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8000008c <test5_data>:
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8000008c: 0038 addi a4,sp,8
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...
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80000090 <test6_data>:
|
||||
80000090: 0000004b fnmsub.s ft0,ft0,ft0,ft0,rne
|
||||
|
||||
80000094 <test7_data>:
|
||||
80000094: 0038 addi a4,sp,8
|
||||
...
|
||||
|
||||
80000098 <test8_data>:
|
||||
80000098: 00000053 fadd.s ft0,ft0,ft0,rne
|
||||
|
||||
8000009c <test9_data>:
|
||||
8000009c: 0021 c.nop 8
|
||||
...
|
||||
|
||||
800000a0 <test10_data>:
|
||||
800000a0: ffffffbf 0xffffffbf
|
||||
|
||||
800000a4 <test11_data>:
|
||||
800000a4: ffa9 bnez a5,7ffffffe <_start-0x2>
|
||||
800000a6: ffff 0xffff
|
||||
|
||||
800000a8 <test12_data>:
|
||||
800000a8: ffc9 bnez a5,80000042 <count_thread_wait+0x1e>
|
||||
800000aa: ffff 0xffff
|
||||
|
||||
800000ac <test13_data>:
|
||||
800000ac: 0004 0x4
|
||||
800000ae: ffff 0xffff
|
||||
|
||||
800000b0 <test14_data>:
|
||||
800000b0: 0005 c.nop 1
|
||||
800000b2: ffff 0xffff
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -1,19 +1,20 @@
|
|||
#define REPORT_OFFSET 0xF0000000
|
||||
#define REPORT_THREAD_ID 0
|
||||
#define REPORT_THREAD_COUNT 1
|
||||
#define REPORT_SUCCESS 2
|
||||
#define REPORT_FAILURE 3
|
||||
#define REPORT_OFFSET 0xF8000000
|
||||
#define REPORT_THREAD_ID 0x00
|
||||
#define REPORT_THREAD_COUNT 0x04
|
||||
#define REPORT_END 0x08
|
||||
#define REPORT_BARRIER_START 0x0C
|
||||
#define REPORT_BARRIER_END 0x10
|
||||
|
||||
#define report(reg, id) \
|
||||
li a0, id*4; \
|
||||
sw reg, 0(a0); \
|
||||
li t0, REPORT_OFFSET+id; \
|
||||
csrr t1, mhartid; \
|
||||
slli t1, t1, 16; \
|
||||
add t0, t0, t1; \
|
||||
sw reg, 0(t0); \
|
||||
|
||||
_start:
|
||||
|
||||
#define HART_ID x20
|
||||
csrr HART_ID, mhartid
|
||||
la a0, test1_data
|
||||
report(a0, REPORT_THREAD_ID)
|
||||
csrr s0, mhartid
|
||||
report(s0, REPORT_THREAD_ID)
|
||||
|
||||
|
||||
count_thread_start:
|
||||
|
|
@ -29,16 +30,88 @@ count_thread_wait:
|
|||
call sleep
|
||||
lw s1, thread_count
|
||||
bne s1, s0, count_thread_wait
|
||||
report(s1, REPORT_THREAD_ID)
|
||||
report(s1, REPORT_THREAD_COUNT)
|
||||
|
||||
|
||||
barrier_amo_test:
|
||||
li a0, 1
|
||||
call barrier_amo
|
||||
li a0, 2
|
||||
call barrier_amo
|
||||
li a0, 3
|
||||
call barrier_amo
|
||||
|
||||
li a0, 4
|
||||
call barrier_lrsc
|
||||
li a0, 5
|
||||
call barrier_lrsc
|
||||
li a0, 6
|
||||
call barrier_lrsc
|
||||
|
||||
li a0, 7
|
||||
call barrier_amo
|
||||
li a0, 8
|
||||
call barrier_lrsc
|
||||
|
||||
|
||||
j success
|
||||
|
||||
|
||||
|
||||
|
||||
barrier_amo:
|
||||
report(a0, REPORT_BARRIER_START)
|
||||
la t0, barrier_amo_value
|
||||
li t1, 1
|
||||
amoadd.w x0, t1, (t0)
|
||||
lw t1, thread_count
|
||||
barrier_amo_wait:
|
||||
lw t2, (t0)
|
||||
bne t2, t1, barrier_amo_wait
|
||||
report(a0, REPORT_BARRIER_END)
|
||||
barrier_amo_reset:
|
||||
csrr t0, mhartid
|
||||
bnez t0, barrier_amo_reset_wait
|
||||
sw x0, barrier_amo_value, t0
|
||||
ret
|
||||
barrier_amo_reset_wait:
|
||||
lw t0, barrier_amo_value
|
||||
bnez t0, barrier_amo_reset_wait
|
||||
ret
|
||||
|
||||
barrier_lrsc:
|
||||
report(a0, REPORT_BARRIER_START)
|
||||
la t0, barrier_lrsc_value
|
||||
barrier_lrsc_try:
|
||||
lr.w t1, (t0)
|
||||
addi t1, t1, 1
|
||||
sc.w t1, t1, (t0)
|
||||
bnez t1, barrier_lrsc_try
|
||||
lw t1, thread_count
|
||||
barrier_lrsc_wait:
|
||||
lw t2, (t0)
|
||||
bne t2, t1, barrier_lrsc_wait
|
||||
report(a0, REPORT_BARRIER_END)
|
||||
barrier_lrsc_reset:
|
||||
csrr t0, mhartid
|
||||
bnez t0, barrier_lrsc_reset_wait
|
||||
sw x0, barrier_lrsc_value, t0
|
||||
ret
|
||||
barrier_lrsc_reset_wait:
|
||||
lw t0, barrier_lrsc_value
|
||||
bnez t0, barrier_lrsc_reset_wait
|
||||
ret
|
||||
|
||||
|
||||
|
||||
success:
|
||||
report(x0, REPORT_SUCCESS)
|
||||
li s0, 0
|
||||
report(s0, REPORT_END)
|
||||
j end
|
||||
|
||||
failure:
|
||||
report(x0, REPORT_FAILURE)
|
||||
li s0, 1
|
||||
report(s0, REPORT_END)
|
||||
j end
|
||||
|
||||
end:
|
||||
|
|
@ -53,18 +126,5 @@ sleep:
|
|||
|
||||
thread_count: .word 0
|
||||
shared_memory_1: .word 0
|
||||
|
||||
test1_data: .word 11
|
||||
test2_data: .word 22
|
||||
test3_data: .word 73
|
||||
test4_data: .word 58
|
||||
test5_data: .word 56
|
||||
test6_data: .word 75
|
||||
test7_data: .word 56
|
||||
test8_data: .word 83
|
||||
test9_data: .word 33
|
||||
test10_data: .word -65
|
||||
test11_data: .word -87
|
||||
test12_data: .word -55
|
||||
test13_data: .word 0xFFFF0004
|
||||
test14_data: .word 0xFFFF0005
|
||||
barrier_amo_value: .word 0
|
||||
barrier_lrsc_value: .word 0
|
||||
|
|
|
|||
Loading…
Reference in New Issue