Add dummy decoding, exception code/tval
Add Cpu generation code Add support for always ready rsp
This commit is contained in:
Charles Papon
parent
5ac443b745
commit
d94cee13f0
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@ -0,0 +1,76 @@
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package vexriscv.demo
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import spinal.core._
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import vexriscv.plugin._
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import vexriscv.{VexRiscv, VexRiscvConfig, plugin}
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/**
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* Created by spinalvm on 15.06.17.
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*/
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object GenSmallAndProductiveCfu extends App{
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def cpu() = new VexRiscv(
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config = VexRiscvConfig(
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plugins = List(
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new IBusSimplePlugin(
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resetVector = 0x80000000l,
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cmdForkOnSecondStage = false,
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cmdForkPersistence = false,
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prediction = NONE,
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catchAccessFault = false,
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compressedGen = false
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),
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new DBusSimplePlugin(
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catchAddressMisaligned = false,
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catchAccessFault = false
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),
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new CsrPlugin(CsrPluginConfig.smallest),
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new DecoderSimplePlugin(
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catchIllegalInstruction = false
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),
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new RegFilePlugin(
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regFileReadyKind = plugin.SYNC,
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zeroBoot = false
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),
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new IntAluPlugin,
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new SrcPlugin(
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separatedAddSub = false,
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executeInsertion = true
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),
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new LightShifterPlugin,
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new HazardSimplePlugin(
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bypassExecute = true,
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bypassMemory = true,
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bypassWriteBack = true,
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bypassWriteBackBuffer = true,
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pessimisticUseSrc = false,
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pessimisticWriteRegFile = false,
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pessimisticAddressMatch = false
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),
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new BranchPlugin(
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earlyBranch = false,
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catchAddressMisaligned = false
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),
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new CfuPlugin(
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p = CfuParameter(
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stageCount = 1,
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allowZeroLatency = true,
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CFU_VERSION = 0,
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CFU_INTERFACE_ID_W = 0,
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CFU_FUNCTION_ID_W = 2,
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CFU_REORDER_ID_W = 0,
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CFU_REQ_RESP_ID_W = 0,
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CFU_INPUTS = 2,
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CFU_INPUT_DATA_W = 32,
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CFU_OUTPUTS = 1,
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CFU_OUTPUT_DATA_W = 32,
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CFU_FLOW_REQ_READY_ALWAYS = false,
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CFU_FLOW_RESP_READY_ALWAYS = false
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)
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),
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new YamlPlugin("cpu0.yaml")
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)
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)
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)
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SpinalVerilog(cpu())
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}
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@ -1,12 +1,11 @@
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package vexriscv.plugin
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import vexriscv.{DecoderService, Stageable, VexRiscv}
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import vexriscv.{DecoderService, ExceptionCause, ExceptionService, Stage, Stageable, VexRiscv}
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import spinal.core._
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import spinal.lib._
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case class CfuParameter(stageCount : Int,
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allowZeroLatency : Boolean,
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dropWidth : Int,
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CFU_VERSION : Int,
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CFU_INTERFACE_ID_W : Int,
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CFU_FUNCTION_ID_W : Int,
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@ -16,8 +15,8 @@ case class CfuParameter(stageCount : Int,
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CFU_INPUT_DATA_W : Int,
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CFU_OUTPUTS : Int,
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CFU_OUTPUT_DATA_W : Int,
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CFU_FLOW_REQ_READY_ALWAYS : Int,
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CFU_FLOW_RESP_READY_ALWAYS : Int)
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CFU_FLOW_REQ_READY_ALWAYS : Boolean,
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CFU_FLOW_RESP_READY_ALWAYS : Boolean)
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case class CfuCmd(p : CfuParameter) extends Bundle{
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val function_id = UInt(p.CFU_FUNCTION_ID_W bits)
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@ -33,12 +32,10 @@ case class CfuRsp(p : CfuParameter) extends Bundle{
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}
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case class CfuBus(p : CfuParameter) extends Bundle with IMasterSlave{
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val interface_id = UInt(p.CFU_INTERFACE_ID_W bits)
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val cmd = Stream(CfuCmd(p))
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val rsp = Stream(CfuRsp(p))
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override def asMaster(): Unit = {
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out(interface_id)
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master(cmd)
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slave(rsp)
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}
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@ -47,39 +44,46 @@ case class CfuBus(p : CfuParameter) extends Bundle with IMasterSlave{
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class CfuPlugin(val p: CfuParameter) extends Plugin[VexRiscv]{
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assert(p.CFU_INPUTS <= 2)
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assert(p.CFU_OUTPUTS == 1)
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assert(p.CFU_FLOW_REQ_READY_ALWAYS == false)
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assert(p.CFU_FLOW_RESP_READY_ALWAYS == false)
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var bus : CfuBus = null
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var joinException : Flow[ExceptionCause] = null
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lazy val forkStage = pipeline.execute
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lazy val joinStage = pipeline.stages(Math.min(pipeline.stages.length - 1, pipeline.indexOf(forkStage) + p.stageCount - 1))
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object CFU_ENABLE extends Stageable(Bool())
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object CFU_FUNCTION extends Stageable(UInt(p.CFU_FUNCTION_ID_W bits))
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object CFU_IN_FLIGHT extends Stageable(Bool())
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override def setup(pipeline: VexRiscv): Unit = {
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import pipeline._
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import pipeline.config._
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bus = CfuBus(p)
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bus = master(CfuBus(p))
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joinException = pipeline.service(classOf[ExceptionService]).newExceptionPort(joinStage)
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val decoderService = pipeline.service(classOf[DecoderService])
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//custom-0
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decoderService.add(List(
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M"000000-----------000-----0010011" -> List(
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M"000000-----------000-----0001011" -> List(
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CFU_ENABLE -> True,
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CFU_FUNCTION -> U"00",
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REGFILE_WRITE_VALID -> ???,
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BYPASSABLE_EXECUTE_STAGE -> ???,
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BYPASSABLE_MEMORY_STAGE -> ???,
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RS1_USE -> ???,
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RS2_USE -> ???
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REGFILE_WRITE_VALID -> True,
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BYPASSABLE_EXECUTE_STAGE -> Bool(p.stageCount == 0),
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BYPASSABLE_MEMORY_STAGE -> Bool(p.stageCount <= 1),
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RS1_USE -> True,
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RS2_USE -> True
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),
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M"000000-----------001-----0010011" -> List(
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M"000000-----------001-----0001011" -> List(
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CFU_ENABLE -> True,
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CFU_FUNCTION -> U"01",
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REGFILE_WRITE_VALID -> ???,
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BYPASSABLE_EXECUTE_STAGE -> ???,
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BYPASSABLE_MEMORY_STAGE -> ???,
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RS1_USE -> ???,
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RS2_USE -> ???
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REGFILE_WRITE_VALID -> True,
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BYPASSABLE_EXECUTE_STAGE -> Bool(p.stageCount == 0),
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BYPASSABLE_MEMORY_STAGE -> Bool(p.stageCount <= 1),
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RS1_USE -> True,
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RS2_USE -> True
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)
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))
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}
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@ -88,10 +92,6 @@ class CfuPlugin(val p: CfuParameter) extends Plugin[VexRiscv]{
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import pipeline._
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import pipeline.config._
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val forkStage = execute
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val joinStageId = Math.min(stages.length - 1, pipeline.indexOf(execute) + p.stageCount - 1)
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val joinStage = stages(joinStageId)
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forkStage plug new Area{
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import forkStage._
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val schedule = arbitration.isValid && input(CFU_ENABLE)
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@ -114,13 +114,30 @@ class CfuPlugin(val p: CfuParameter) extends Plugin[VexRiscv]{
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//If the CFU interface can produce a result combinatorialy and the fork stage isn't the same than the join stage
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//Then it is required to add a buffer on rsp to not propagate the fork stage ready := False in the CPU pipeline.
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val rsp = if(forkStage != joinStage && p.allowZeroLatency) bus.rsp.m2sPipe() else bus.rsp
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val rsp = if(p.CFU_FLOW_RESP_READY_ALWAYS){
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bus.rsp.toFlow.toStream.queueLowLatency(
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size = p.stageCount + 1,
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latency = 0
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)
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} else if(forkStage != joinStage && p.allowZeroLatency) {
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bus.rsp.m2sPipe()
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} else {
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bus.rsp.combStage()
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}
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joinException.valid := False
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joinException.code := 15
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joinException.badAddr := 0
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rsp.ready := False
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when(input(CFU_IN_FLIGHT)){
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arbitration.haltItself setWhen(!rsp.valid)
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rsp.ready := arbitration.isStuckByOthers
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output(REGFILE_WRITE_DATA) := rsp.outputs(0)
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when(arbitration.isValid){
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joinException.valid := !rsp.response_ok
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}
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}
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}
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}
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