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VexRiscv
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statuc prediction is fully funcitonnal

This commit is contained in:
Dolu1990 2018-04-02 17:43:58 +02:00
parent 76ca852478
commit d9f2e03753
2 changed files with 5 additions and 4 deletions
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4
src/main/scala/vexriscv/plugin/BranchPlugin.scala
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@ -278,7 +278,7 @@ class BranchPlugin(earlyBranch : Boolean,
}
default{
branch_src1 := input(PC)
branch_src2 := (input(PREDICTION_HAD_BRANCHED) ? B(4) | imm.b_sext).asUInt
branch_src2 := (input(PREDICTION_HAD_BRANCHED) ? (if(pipeline(RVC_GEN)) Mux(input(IS_RVC), B(2), B(4)) else B(4)).resized | imm.b_sext).asUInt
}
}
val branchAdder = branch_src1 + branch_src2
@ -298,7 +298,7 @@ class BranchPlugin(earlyBranch : Boolean,
}
if(catchAddressMisaligned) {
branchExceptionPort.valid := input(INSTRUCTION_READY) && arbitration.isValid && input(BRANCH_DO) && jumpInterface.payload(1 downto 0) =/= 0
branchExceptionPort.valid := arbitration.isValid && input(BRANCH_DO) && (if(pipeline(RVC_GEN)) jumpInterface.payload(0 downto 0) =/= 0 else jumpInterface.payload(1 downto 0) =/= 0)
branchExceptionPort.code := 0
branchExceptionPort.badAddr := jumpInterface.payload
}

5
src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
View File

@ -110,13 +110,14 @@ class IBusSimplePlugin(interfaceKeepData : Boolean, catchAccessFault : Boolean,
var prefetchExceptionPort : Flow[ExceptionCause] = null
def resetVector = BigInt(0x80000000l)
def keepPcPlus4 = false
def decodePcGen = false
def compressedGen = false
def decodePcGen = true
def compressedGen = true
def cmdToRspStageCount = 1
def rspStageGen = false
def injectorReadyCutGen = false
def relaxedPcCalculation = false
def prediction : BranchPrediction = STATIC
def catchAddressMisaligned = true
var decodePrediction : DecodePredictionBus = null
assert(cmdToRspStageCount >= 1)
assert(!(compressedGen && !decodePcGen))