Add VexRiscvLitexSmpClusterCmdGen
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@ -11,7 +11,8 @@ import vexriscv.plugin.DBusCachedPlugin
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case class VexRiscvLitexSmpClusterParameter( cluster : VexRiscvSmpClusterParameter,
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liteDram : LiteDramNativeParameter,
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liteDramMapping : AddressMapping)
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liteDramMapping : AddressMapping,
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coherentDma : Boolean)
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class VexRiscvLitexSmpCluster(p : VexRiscvLitexSmpClusterParameter) extends VexRiscvSmpClusterWithPeripherals(p.cluster) {
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@ -24,21 +25,24 @@ class VexRiscvLitexSmpCluster(p : VexRiscvLitexSmpClusterParameter) extends VexR
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iArbiter.bmb -> List(iBridge.bmb, peripheralBridge.bmb),
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invalidationMonitor.output -> List(dBridge.bmb, peripheralBridge.bmb)
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)
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interconnect.masters(invalidationMonitor.output).withOutOfOrderDecoder()
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if(p.coherentDma || p.cluster.cpuConfigs.size > 1) interconnect.masters(invalidationMonitor.output).withOutOfOrderDecoder()
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dBridge.liteDramParameter.load(p.liteDram)
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iBridge.liteDramParameter.load(p.liteDram)
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// Coherent DMA interface
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val dmaBridge = WishboneToBmbGenerator()
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val dmaWishbone = dmaBridge.produceIo(dmaBridge.logic.io.input)
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val dmaDataWidth = p.cluster.cpuConfigs.head.find(classOf[DBusCachedPlugin]).get.config.memDataWidth
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dmaBridge.config.load(WishboneConfig(
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addressWidth = 32-log2Up(dmaDataWidth/8),
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val dma = p.coherentDma generate new Area {
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val bridge = WishboneToBmbGenerator()
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val wishbone = bridge.produceIo(bridge.logic.io.input)
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val dataWidth = p.cluster.cpuConfigs.head.find(classOf[DBusCachedPlugin]).get.config.memDataWidth
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bridge.config.load(WishboneConfig(
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addressWidth = 32 - log2Up(dataWidth / 8),
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dataWidth = p.cluster.cpuConfigs.head.find(classOf[DBusCachedPlugin]).get.config.memDataWidth,
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useSTALL = true
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))
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interconnect.addConnection(dmaBridge.bmb, exclusiveMonitor.input)
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interconnect.addConnection(bridge.bmb, exclusiveMonitor.input)
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}
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// Interconnect pipelining (FMax)
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for(core <- cores) {
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@ -51,6 +55,55 @@ class VexRiscvLitexSmpCluster(p : VexRiscvLitexSmpClusterParameter) extends VexR
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}
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object VexRiscvLitexSmpClusterCmdGen extends App {
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var cpuCount = 1
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var iBusWidth = 64
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var dBusWidth = 64
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var liteDramWidth = 128
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var coherentDma = false
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var netlistDirectory = "."
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var netlistName = "VexRiscvLitexSmpCluster"
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assert(new scopt.OptionParser[Unit]("VexRiscvLitexSmpClusterCmdGen") {
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help("help").text("prints this usage text")
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opt[Unit]("coherent-dma") action { (v, c) => coherentDma = true }
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opt[String]("cpu-count") action { (v, c) => cpuCount = v.toInt }
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opt[String]("ibus-width") action { (v, c) => iBusWidth = v.toInt }
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opt[String]("dbus-width") action { (v, c) => dBusWidth = v.toInt }
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opt[String]("litedram-width") action { (v, c) => liteDramWidth = v.toInt }
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opt[String]("netlist-directory") action { (v, c) => netlistDirectory = v }
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opt[String]("netlist-name") action { (v, c) => netlistName = v }
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}.parse(args))
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def parameter = VexRiscvLitexSmpClusterParameter(
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cluster = VexRiscvSmpClusterParameter(
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cpuConfigs = List.tabulate(cpuCount) { hartId =>
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vexRiscvConfig(
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hartId = hartId,
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ioRange = address => address.msb,
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resetVector = 0,
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iBusWidth = iBusWidth,
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dBusWidth = dBusWidth
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)
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}
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),
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liteDram = LiteDramNativeParameter(addressWidth = 32, dataWidth = liteDramWidth),
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liteDramMapping = SizeMapping(0x40000000l, 0x40000000l),
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coherentDma = coherentDma
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)
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def dutGen = {
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val toplevel = new VexRiscvLitexSmpCluster(
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p = parameter
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).toComponent()
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toplevel
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}
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val genConfig = SpinalConfig(targetDirectory = netlistDirectory).addStandardMemBlackboxing(blackboxByteEnables)
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genConfig.generateVerilog(dutGen.setDefinitionName(netlistName))
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}
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object VexRiscvLitexSmpClusterGen extends App {
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for(cpuCount <- List(1,2,4,8)) {
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def parameter = VexRiscvLitexSmpClusterParameter(
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@ -64,7 +117,8 @@ object VexRiscvLitexSmpClusterGen extends App {
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}
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),
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liteDram = LiteDramNativeParameter(addressWidth = 32, dataWidth = 128),
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liteDramMapping = SizeMapping(0x40000000l, 0x40000000l)
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liteDramMapping = SizeMapping(0x40000000l, 0x40000000l),
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coherentDma = false
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)
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def dutGen = {
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@ -101,7 +155,8 @@ object VexRiscvLitexSmpClusterOpenSbi extends App{
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}
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),
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liteDram = LiteDramNativeParameter(addressWidth = 32, dataWidth = 128),
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liteDramMapping = SizeMapping(0x80000000l, 0x70000000l)
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liteDramMapping = SizeMapping(0x80000000l, 0x70000000l),
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coherentDma = false
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)
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def dutGen = {
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