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Cleanup BmbGenerators

This commit is contained in:
Dolu1990 2020-07-15 20:51:46 +02:00
parent 5f0aec7570
commit da73317912
2 changed files with 2 additions and 2 deletions
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2
src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala
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@ -15,7 +15,7 @@ case class VexRiscvLitexSmpClusterParameter( cluster : VexRiscvSmpClusterParamet
class VexRiscvLitexSmpCluster(p : VexRiscvLitexSmpClusterParameter) extends VexRiscvSmpClusterWithPeripherals(p.cluster) { class VexRiscvLitexSmpCluster(p : VexRiscvLitexSmpClusterParameter) extends VexRiscvSmpClusterWithPeripherals(p.cluster) {
val iArbiter = BmbSmpBridgeGenerator() val iArbiter = BmbBridgeGenerator()
val iBridge = BmbToLiteDramGenerator(p.liteDramMapping) val iBridge = BmbToLiteDramGenerator(p.liteDramMapping)
val dBridge = BmbToLiteDramGenerator(p.liteDramMapping) val dBridge = BmbToLiteDramGenerator(p.liteDramMapping)

2
src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexMpCluster.scala
View File

@ -12,7 +12,7 @@ case class VexRiscvLitexSmpMpClusterParameter( cluster : VexRiscvSmpClusterParam
liteDramMapping : AddressMapping) liteDramMapping : AddressMapping)
class VexRiscvLitexSmpMpCluster(p : VexRiscvLitexSmpMpClusterParameter) extends VexRiscvSmpClusterWithPeripherals(p.cluster) { class VexRiscvLitexSmpMpCluster(p : VexRiscvLitexSmpMpClusterParameter) extends VexRiscvSmpClusterWithPeripherals(p.cluster) {
val iArbiter = BmbSmpBridgeGenerator() val iArbiter = BmbBridgeGenerator()
val iBridge = BmbToLiteDramGenerator(p.liteDramMapping) val iBridge = BmbToLiteDramGenerator(p.liteDramMapping)
val dBridge = BmbToLiteDramGenerator(p.liteDramMapping) val dBridge = BmbToLiteDramGenerator(p.liteDramMapping)