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VexRiscv
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Merge branch dev (SpinalHDL 1.6.1)

This commit is contained in:
Dolu1990 2021-12-15 09:22:46 +01:00
parent 68e704f309 0539dd7110
commit dd12047aa7
27 changed files with 719 additions and 236 deletions
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2
build.sbt
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@ -1,4 +1,4 @@
val spinalVersion = "1.6.0"
val spinalVersion = "1.6.1"
lazy val root = (project in file(".")).
settings(

14
src/main/scala/vexriscv/Stage.scala
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@ -14,13 +14,13 @@ class Stageable[T <: Data](_dataType : => T) extends HardType[T](_dataType) with
class Stage() extends Area{
def outsideCondScope[T](that : => T) : T = {
val body = Component.current.dslBody
body.push()
val swapContext = body.swap()
val ret = that
body.pop()
swapContext.appendBack()
ret
val body = Component.current.dslBody // Get the head of the current component symboles tree (AST in other words)
val ctx = body.push() // Now all access to the SpinalHDL API will be append to it (instead of the current context)
val swapContext = body.swap() // Empty the symbole tree (but keep a reference to the old content)
val ret = that // Execute the block of code (will be added to the recently empty body)
ctx.restore() // Restore the original context in which this function was called
swapContext.appendBack() // append the original symboles tree to the modified body
ret // return the value returned by that
}
def input[T <: Data](key : Stageable[T]) : T = {

2
src/main/scala/vexriscv/VexRiscvBmbGenerator.scala
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@ -25,7 +25,7 @@ case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGener
val debugClockDomain = Handle[ClockDomain]
val debugReset = Handle[Bool]
val debugAskReset = Handle[() => Unit]
val hardwareBreakpointCount = Handle(0)
val hardwareBreakpointCount = Handle.sync(0)
val iBus, dBus = Handle[Bmb]

49
src/main/scala/vexriscv/demo/Briey.scala
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@ -9,12 +9,15 @@ import spinal.lib._
import spinal.lib.bus.amba3.apb._
import spinal.lib.bus.amba4.axi._
import spinal.lib.com.jtag.Jtag
import spinal.lib.com.jtag.sim.JtagTcp
import spinal.lib.com.uart.sim.{UartDecoder, UartEncoder}
import spinal.lib.com.uart.{Apb3UartCtrl, Uart, UartCtrlGenerics, UartCtrlMemoryMappedConfig}
import spinal.lib.graphic.RgbConfig
import spinal.lib.graphic.vga.{Axi4VgaCtrl, Axi4VgaCtrlGenerics, Vga}
import spinal.lib.io.TriStateArray
import spinal.lib.memory.sdram.SdramGeneration.SDR
import spinal.lib.memory.sdram._
import spinal.lib.memory.sdram.sdr.sim.SdramModel
import spinal.lib.memory.sdram.sdr.{Axi4SharedSdramCtrl, IS42x320D, SdramInterface, SdramTimings}
import spinal.lib.misc.HexTools
import spinal.lib.soc.pinsec.{PinsecTimerCtrl, PinsecTimerCtrlExternal}
@ -160,7 +163,7 @@ object BrieyConfig{
class Briey(config: BrieyConfig) extends Component{
class Briey(val config: BrieyConfig) extends Component{
//Legacy constructor
def this(axiFrequency: HertzNumber) {
@ -200,7 +203,7 @@ class Briey(config: BrieyConfig) extends Component{
val resetCtrl = new ClockingArea(resetCtrlClockDomain) {
val systemResetUnbuffered = False
// val coreResetUnbuffered = False
// val coreResetUnbuffered = False
//Implement an counter to keep the reset axiResetOrder high 64 cycles
// Also this counter will automaticly do a reset when the system boot.
@ -270,6 +273,7 @@ class Briey(config: BrieyConfig) extends Component{
val uartCtrl = Apb3UartCtrl(uartCtrlConfig)
uartCtrl.io.apb.addAttribute(Verilator.public)
val vgaCtrlConfig = Axi4VgaCtrlGenerics(
@ -443,3 +447,44 @@ object BrieyDe0Nano{
})
}
}
import spinal.core.sim._
object BrieySim {
def main(args: Array[String]): Unit = {
val simSlowDown = false
SimConfig.allOptimisation.compile(new Briey(BrieyConfig.default)).doSimUntilVoid{dut =>
val mainClkPeriod = (1e12/dut.config.axiFrequency.toDouble).toLong
val jtagClkPeriod = mainClkPeriod*4
val uartBaudRate = 115200
val uartBaudPeriod = (1e12/uartBaudRate).toLong
val clockDomain = ClockDomain(dut.io.axiClk, dut.io.asyncReset)
clockDomain.forkStimulus(mainClkPeriod)
val tcpJtag = JtagTcp(
jtag = dut.io.jtag,
jtagClkPeriod = jtagClkPeriod
)
val uartTx = UartDecoder(
uartPin = dut.io.uart.txd,
baudPeriod = uartBaudPeriod
)
val uartRx = UartEncoder(
uartPin = dut.io.uart.rxd,
baudPeriod = uartBaudPeriod
)
val sdram = SdramModel(
dut.io.sdram,
dut.config.sdramLayout,
clockDomain
)
dut.io.coreInterrupt #= false
}
}
}

64
src/main/scala/vexriscv/demo/GenSmallAndProductiveVfu.scala Normal file
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@ -0,0 +1,64 @@
package vexriscv.demo
import spinal.core._
import vexriscv.plugin._
import vexriscv.{VexRiscv, VexRiscvConfig, plugin}
/**
* Created by spinalvm on 15.06.17.
*/
object GenSmallAndProductiveVfu extends App{
def cpu() = new VexRiscv(
config = VexRiscvConfig(
plugins = List(
new IBusSimplePlugin(
resetVector = 0x80000000l,
cmdForkOnSecondStage = false,
cmdForkPersistence = false,
prediction = NONE,
catchAccessFault = false,
compressedGen = false
),
new DBusSimplePlugin(
catchAddressMisaligned = false,
catchAccessFault = false
),
new CsrPlugin(CsrPluginConfig.smallest),
new DecoderSimplePlugin(
catchIllegalInstruction = false
),
new RegFilePlugin(
regFileReadyKind = plugin.SYNC,
zeroBoot = false
),
new IntAluPlugin,
new SrcPlugin(
separatedAddSub = false,
executeInsertion = true
),
new LightShifterPlugin,
new HazardSimplePlugin(
bypassExecute = true,
bypassMemory = true,
bypassWriteBack = true,
bypassWriteBackBuffer = true,
pessimisticUseSrc = false,
pessimisticWriteRegFile = false,
pessimisticAddressMatch = false
),
new BranchPlugin(
earlyBranch = false,
catchAddressMisaligned = false
),
new VfuPlugin(
stageCount = 2,
allowZeroLatency = false,
parameter = VfuParameter()
),
new YamlPlugin("cpu0.yaml")
)
)
)
SpinalVerilog(cpu())
}

1
src/main/scala/vexriscv/demo/VexRiscvCachedWishboneForSim.scala
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@ -64,6 +64,7 @@ object VexRiscvCachedWishboneForSim{
catchIllegal = true,
catchUnaligned = true
),
dBusCmdMasterPipe = true, //required for wishbone
memoryTranslatorPortConfig = null
// memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
// portTlbSize = 6

30
src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
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@ -43,9 +43,9 @@ class VexRiscvSmpClusterBase(p : VexRiscvSmpClusterParameter) extends Area with
systemCd.setInput(debugCd)
systemCd.outputClockDomain.push()
val ctx = systemCd.outputClockDomain.push()
override def postInitCallback(): VexRiscvSmpClusterBase.this.type = {
systemCd.outputClockDomain.pop()
ctx.restore()
this
}
@ -175,6 +175,7 @@ object VexRiscvSmpClusterGen {
iBusRelax : Boolean = false,
injectorStage : Boolean = false,
earlyBranch : Boolean = false,
earlyShifterInjection : Boolean = true,
dBusCmdMasterPipe : Boolean = false,
withMmu : Boolean = true,
withSupervisor : Boolean = true,
@ -188,7 +189,9 @@ object VexRiscvSmpClusterGen {
rvc : Boolean = false,
iTlbSize : Int = 4,
dTlbSize : Int = 4,
prediction : BranchPrediction = vexriscv.plugin.NONE
prediction : BranchPrediction = vexriscv.plugin.NONE,
withDataCache : Boolean = true,
withInstructionCache : Boolean = true
) = {
assert(iCacheSize/iCacheWays <= 4096, "Instruction cache ways can't be bigger than 4096 bytes")
assert(dCacheSize/dCacheWays <= 4096, "Data cache ways can't be bigger than 4096 bytes")
@ -228,7 +231,7 @@ object VexRiscvSmpClusterGen {
ioRange = ioRange
),
//Uncomment the whole IBusCachedPlugin and comment IBusSimplePlugin if you want cached iBus config
new IBusCachedPlugin(
if(withInstructionCache) new IBusCachedPlugin(
resetVector = resetVector,
compressedGen = rvc,
prediction = prediction,
@ -256,8 +259,17 @@ object VexRiscvSmpClusterGen {
earlyRequireMmuLockup = true,
earlyCacheHits = true
)
) else new IBusSimplePlugin(
resetVector = resetVector,
cmdForkOnSecondStage = false,
cmdForkPersistence = false,
prediction = NONE,
catchAccessFault = false,
compressedGen = rvc,
busLatencyMin = 2,
vecRspBuffer = true
),
new DBusCachedPlugin(
if(withDataCache) new DBusCachedPlugin(
dBusCmdMasterPipe = dBusCmdMasterPipe || dBusWidth == 32,
dBusCmdSlavePipe = true,
dBusRspSlavePipe = true,
@ -274,7 +286,7 @@ object VexRiscvSmpClusterGen {
catchUnaligned = true,
withLrSc = atomic,
withAmo = atomic,
withExclusive = atomic,
withExclusive = coherency,
withInvalidate = coherency,
withWriteAggregation = dBusWidth > 32
),
@ -284,6 +296,10 @@ object VexRiscvSmpClusterGen {
earlyRequireMmuLockup = true,
earlyCacheHits = true
)
) else new DBusSimplePlugin(
catchAddressMisaligned = false,
catchAccessFault = false,
earlyInjection = false
),
new DecoderSimplePlugin(
catchIllegalInstruction = true,
@ -299,7 +315,7 @@ object VexRiscvSmpClusterGen {
new SrcPlugin(
separatedAddSub = false
),
new FullBarrelShifterPlugin(earlyInjection = true),
new FullBarrelShifterPlugin(earlyInjection = earlyShifterInjection),
// new LightShifterPlugin,
new HazardSimplePlugin(
bypassExecute = true,

19
src/main/scala/vexriscv/ip/DataCache.scala
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@ -77,9 +77,9 @@ case class DataCacheConfig(cacheSize : Int,
)
def getWishboneConfig() = WishboneConfig(
addressWidth = 30,
dataWidth = 32,
selWidth = 4,
addressWidth = 32-log2Up(memDataWidth/8),
dataWidth = memDataWidth,
selWidth = memDataBytes,
useSTALL = false,
useLOCK = false,
useERR = true,
@ -100,11 +100,11 @@ case class DataCacheConfig(cacheSize : Int,
contextWidth = (if(!withWriteResponse) 1 else 0) + aggregationWidth,
alignment = BmbParameter.BurstAlignement.LENGTH,
canExclusive = withExclusive,
withCachedRead = true
withCachedRead = true,
canInvalidate = withInvalidate,
canSync = withInvalidate
)),
BmbInvalidationParameter(
canInvalidate = withInvalidate,
canSync = withInvalidate,
invalidateLength = log2Up(this.bytePerLine),
invalidateAlignment = BmbParameter.BurstAlignement.LENGTH
)
@ -329,11 +329,12 @@ case class DataCacheMemBus(p : DataCacheConfig) extends Bundle with IMasterSlave
val wishboneConfig = p.getWishboneConfig()
val bus = Wishbone(wishboneConfig)
val counter = Reg(UInt(log2Up(p.burstSize) bits)) init(0)
val addressShift = log2Up(p.memDataWidth/8)
val cmdBridge = Stream (DataCacheMemCmd(p))
val isBurst = cmdBridge.isBurst
cmdBridge.valid := cmd.valid
cmdBridge.address := (isBurst ? (cmd.address(31 downto widthOf(counter) + 2) @@ counter @@ U"00") | (cmd.address(31 downto 2) @@ U"00"))
cmdBridge.address := (isBurst ? (cmd.address(31 downto widthOf(counter) + addressShift) @@ counter @@ U(0, addressShift bits)) | (cmd.address(31 downto addressShift) @@ U(0, addressShift bits)))
cmdBridge.wr := cmd.wr
cmdBridge.mask := cmd.mask
cmdBridge.data := cmd.data
@ -350,10 +351,10 @@ case class DataCacheMemBus(p : DataCacheConfig) extends Bundle with IMasterSlave
}
bus.ADR := cmdBridge.address >> 2
bus.ADR := cmdBridge.address >> addressShift
bus.CTI := Mux(isBurst, cmdBridge.last ? B"111" | B"010", B"000")
bus.BTE := B"00"
bus.SEL := cmdBridge.wr ? cmdBridge.mask | B"1111"
bus.SEL := cmdBridge.wr ? cmdBridge.mask | B((1 << p.memDataBytes)-1)
bus.WE := cmdBridge.wr
bus.DAT_MOSI := cmdBridge.data

10
src/main/scala/vexriscv/ip/InstructionCache.scala
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@ -56,9 +56,9 @@ case class InstructionCacheConfig( cacheSize : Int,
)
def getWishboneConfig() = WishboneConfig(
addressWidth = 30,
dataWidth = 32,
selWidth = 4,
addressWidth = 32-log2Up(memDataWidth/8),
dataWidth = memDataWidth,
selWidth = memDataWidth/8,
useSTALL = false,
useLOCK = false,
useERR = true,
@ -228,10 +228,10 @@ case class InstructionCacheMemBus(p : InstructionCacheConfig) extends Bundle wit
val pending = counter =/= 0
val lastCycle = counter === counter.maxValue
bus.ADR := (cmd.address >> widthOf(counter) + 2) @@ counter
bus.ADR := (cmd.address >> widthOf(counter) + log2Up(p.memDataWidth/8)) @@ counter
bus.CTI := lastCycle ? B"111" | B"010"
bus.BTE := "00"
bus.SEL := "1111"
bus.SEL.setAll()
bus.WE := False
bus.DAT_MOSI.assignDontCare()
bus.CYC := False

6
src/main/scala/vexriscv/plugin/CfuPlugin.scala
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@ -166,7 +166,11 @@ class CfuPlugin(val stageCount : Int,
forkStage plug new Area{
import forkStage._
val schedule = arbitration.isValid && input(CFU_ENABLE)
val hazard = stages.dropWhile(_ != forkStage).tail.map(s => s.arbitration.isValid && s.input(HAS_SIDE_EFFECT)).orR
val scheduleWish = arbitration.isValid && input(CFU_ENABLE)
val schedule = scheduleWish && !hazard
arbitration.haltItself setWhen(scheduleWish && hazard)
val hold = RegInit(False) setWhen(schedule) clearWhen(bus.cmd.ready)
val fired = RegInit(False) setWhen(bus.cmd.fire) clearWhen(!arbitration.isStuckByOthers)
insert(CFU_IN_FLIGHT) := schedule || hold || fired

18
src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
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@ -81,8 +81,9 @@ class DBusCachedPlugin(val config : DataCacheConfig,
// REGFILE_WRITE_VALID -> True,
// BYPASSABLE_EXECUTE_STAGE -> False,
// BYPASSABLE_MEMORY_STAGE -> False,
MEMORY_WR -> False
) ++ (if(catchSomething) List(HAS_SIDE_EFFECT -> True) else Nil)
MEMORY_WR -> False,
HAS_SIDE_EFFECT -> True
)
)
if(withLrSc) decoderService.add(key, Seq(MEMORY_LRSC -> False))
@ -103,8 +104,9 @@ class DBusCachedPlugin(val config : DataCacheConfig,
IntAluPlugin.ALU_CTRL -> IntAluPlugin.AluCtrlEnum.ADD_SUB,
SRC2_CTRL -> Src2CtrlEnum.IMS,
// RS2_USE -> True,
MEMORY_WR -> True
) ++ (if(catchSomething) List(HAS_SIDE_EFFECT -> True) else Nil)
MEMORY_WR -> True,
HAS_SIDE_EFFECT -> True
)
)
if(withLrSc) decoderService.add(key, Seq(MEMORY_LRSC -> False))
@ -156,13 +158,15 @@ class DBusCachedPlugin(val config : DataCacheConfig,
REGFILE_WRITE_VALID -> True,
BYPASSABLE_EXECUTE_STAGE -> False,
BYPASSABLE_MEMORY_STAGE -> False,
MEMORY_WR -> False
) ++ (if(catchSomething) List(HAS_SIDE_EFFECT -> True) else Nil)
MEMORY_WR -> False,
HAS_SIDE_EFFECT -> True
)
val storeActions = stdActions ++ List(
SRC2_CTRL -> Src2CtrlEnum.IMS,
RS2_USE -> True,
MEMORY_WR -> True
MEMORY_WR -> True,
HAS_SIDE_EFFECT -> True
)
decoderService.addDefault(MEMORY_ENABLE, False)

8
src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
View File

@ -327,13 +327,15 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false,
REGFILE_WRITE_VALID -> True,
BYPASSABLE_EXECUTE_STAGE -> False,
BYPASSABLE_MEMORY_STAGE -> Bool(earlyInjection),
MEMORY_STORE -> False
) ++ (if(catchAccessFault || catchAddressMisaligned) List(HAS_SIDE_EFFECT -> True) else Nil)
MEMORY_STORE -> False,
HAS_SIDE_EFFECT -> True
)
val storeActions = stdActions ++ List(
SRC2_CTRL -> Src2CtrlEnum.IMS,
RS2_USE -> True,
MEMORY_STORE -> True
MEMORY_STORE -> True,
HAS_SIDE_EFFECT -> True
)
decoderService.addDefault(MEMORY_ENABLE, False)

13
src/main/scala/vexriscv/plugin/DebugPlugin.scala
View File

@ -176,7 +176,7 @@ case class DebugExtensionIo() extends Bundle with IMasterSlave{
}
}
class DebugPlugin(var debugClockDomain : ClockDomain, hardwareBreakpointCount : Int = 0) extends Plugin[VexRiscv] {
class DebugPlugin(var debugClockDomain : ClockDomain, hardwareBreakpointCount : Int = 0, BreakpointReadback : Boolean = false) extends Plugin[VexRiscv] {
var io : DebugExtensionIo = null
val injectionAsks = ArrayBuffer[(Stage, Bool)]()
@ -248,6 +248,17 @@ class DebugPlugin(var debugClockDomain : ClockDomain, hardwareBreakpointCount :
io.bus.rsp.data(3) := haltedByBreak
io.bus.rsp.data(4) := stepIt
}
if (BreakpointReadback) {
switch(RegNext(io.bus.cmd.address(7 downto 2))) {
for(i <- 0 until hardwareBreakpointCount){
is(0x10 + i){
io.bus.rsp.data(31 downto 1) := hardwareBreakpoints(i).pc.asBits
io.bus.rsp.data(0) := hardwareBreakpoints(i).valid
}
}
}
}
injectionPort.valid := False
injectionPort.payload := io.bus.cmd.data

5
src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
View File

@ -236,7 +236,8 @@ class IBusSimplePlugin( resetVector : BigInt,
val memoryTranslatorPortConfig : Any = null,
relaxPredictorAddress : Boolean = true,
predictionBuffer : Boolean = true,
bigEndian : Boolean = false
bigEndian : Boolean = false,
vecRspBuffer : Boolean = false
) extends IBusFetcherImpl(
resetVector = resetVector,
keepPcPlus4 = keepPcPlus4,
@ -351,7 +352,7 @@ class IBusSimplePlugin( resetVector : BigInt,
//Manage flush for iBus transactions in flight
val rspBuffer = new Area {
val output = Stream(IBusSimpleRsp())
val c = StreamFifoLowLatency(IBusSimpleRsp(), busLatencyMin + (if(cmdForkOnSecondStage && cmdForkPersistence) 1 else 0))
val c = new StreamFifoLowLatency(IBusSimpleRsp(), busLatencyMin + (if(cmdForkOnSecondStage && cmdForkPersistence) 1 else 0), useVec = vecRspBuffer)
val discardCounter = Reg(UInt(log2Up(pendingMax + 1) bits)) init (0)
discardCounter := discardCounter - (c.io.pop.valid && discardCounter =/= 0).asUInt
when(iBusRsp.flush) {

4
src/main/scala/vexriscv/plugin/PmpPlugin.scala
View File

@ -90,7 +90,7 @@ class PmpSetter(cutoff : Int) extends Component with Pmp {
val ones = io.addr & ~(io.addr + 1)
io.base := io.addr(xlen - 3 downto cutoff - 2) ^ ones(xlen - 3 downto cutoff - 2)
io.mask := ~ones(xlen - 2 downto cutoff - 1)
io.mask := ~(ones(xlen - 4 downto cutoff - 2) @@ U"1")
}
case class ProtectedMemoryTranslatorPort(bus : MemoryTranslatorBus)
@ -259,7 +259,7 @@ class PmpPlugin(regions : Int, granularity : Int, ioRange : UInt => Bool) extend
}
def getPermission(hits : IndexedSeq[Bool], bit : Int) = {
(hits zip state.pmpcfg).map({ case (i, cfg) => i & cfg(bit) }).orR
MuxOH(OHMasking.first(hits), state.pmpcfg.map(_(bit)))
}
val dGuard = new Area {

244
src/main/scala/vexriscv/plugin/PmpPluginOld.scala Normal file
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@ -0,0 +1,244 @@
/*
* Copyright (c) 2020 Samuel Lindemer <samuel.lindemer@ri.se>
*
* SPDX-License-Identifier: MIT
*/
package vexriscv.plugin
import vexriscv.{VexRiscv, _}
import spinal.core._
import spinal.lib._
import scala.collection.mutable.ArrayBuffer
/* Each 32-bit pmpcfg# register contains four 8-bit configuration sections.
* These section numbers contain flags which apply to regions defined by the
* corresponding pmpaddr# register.
*
* 3 2 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | pmp3cfg | pmp2cfg | pmp1cfg | pmp0cfg | pmpcfg0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | pmp7cfg | pmp6cfg | pmp5cfg | pmp4cfg | pmpcfg2
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*
* 7 6 5 4 3 2 1 0
* +-------+-------+-------+-------+-------+-------+-------+-------+
* | L | 0 | A | X | W | R | pmp#cfg
* +-------+-------+-------+-------+-------+-------+-------+-------+
*
* L: locks configuration until system reset (including M-mode)
* 0: hardwired to zero
* A: 0 = OFF (null region / disabled)
* 1 = TOR (top of range)
* 2 = NA4 (naturally aligned four-byte region)
* 3 = NAPOT (naturally aligned power-of-two region, > 7 bytes)
* X: execute
* W: write
* R: read
*
* TOR: Each 32-bit pmpaddr# register defines the upper bound of the pmp region
* right-shifted by two bits. The lower bound of the region is the previous
* pmpaddr# register. In the case of pmpaddr0, the lower bound is address 0x0.
*
* 3 2 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | address[33:2] | pmpaddr#
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*
* NAPOT: Each 32-bit pmpaddr# register defines the region address and the size
* of the pmp region. The number of concurrent 1s begging at the LSB indicates
* the size of the region as a power of two (e.g. 0x...0 = 8-byte, 0x...1 =
* 16-byte, 0x...11 = 32-byte, etc.).
*
* 3 2 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | address[33:2] |0|1|1|1|1| pmpaddr#
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*
* NA4: This is essentially an edge case of NAPOT where the entire pmpaddr#
* register defines a 4-byte wide region.
*/
case class PmpRegister(previous : PmpRegister) extends Area {
def OFF = 0
def TOR = 1
def NA4 = 2
def NAPOT = 3
val state = new Area {
val r, w, x = Reg(Bool)
val l = RegInit(False)
val a = Reg(UInt(2 bits)) init(0)
val addr = Reg(UInt(32 bits))
}
// CSR writes connect to these signals rather than the internal state
// registers. This makes locking and WARL possible.
val csr = new Area {
val r, w, x = Bool
val l = Bool
val a = UInt(2 bits)
val addr = UInt(32 bits)
}
// Last valid assignment wins; nothing happens if a user-initiated write did
// not occur on this clock cycle.
csr.r := state.r
csr.w := state.w
csr.x := state.x
csr.l := state.l
csr.a := state.a
csr.addr := state.addr
// Computed PMP region bounds
val region = new Area {
val valid, locked = Bool
val start, end = UInt(32 bits)
}
when(~state.l) {
state.r := csr.r
state.w := csr.w
state.x := csr.x
state.l := csr.l
state.a := csr.a
state.addr := csr.addr
if (csr.l == True & csr.a == TOR) {
previous.state.l := True
}
}
val shifted = state.addr |<< 2
val mask = state.addr & ~(state.addr + 1)
val masked = (state.addr & ~mask) |<< 2
// PMP changes take effect two clock cycles after the initial CSR write (i.e.,
// settings propagate from csr -> state -> region).
region.locked := state.l
region.valid := True
switch(csr.a) {
is(TOR) {
if (previous == null) region.start := 0
else region.start := previous.region.end
region.end := shifted
}
is(NA4) {
region.start := shifted
region.end := shifted + 4
}
is(NAPOT) {
region.start := masked
region.end := masked + ((mask + 1) |<< 3)
}
default {
region.start := 0
region.end := shifted
region.valid := False
}
}
}
class PmpPluginOld(regions : Int, ioRange : UInt => Bool) extends Plugin[VexRiscv] with MemoryTranslator {
// Each pmpcfg# CSR configures four regions.
assert((regions % 4) == 0)
val pmps = ArrayBuffer[PmpRegister]()
val portsInfo = ArrayBuffer[ProtectedMemoryTranslatorPort]()
override def newTranslationPort(priority : Int, args : Any): MemoryTranslatorBus = {
val port = ProtectedMemoryTranslatorPort(MemoryTranslatorBus(new MemoryTranslatorBusParameter(0, 0)))
portsInfo += port
port.bus
}
override def build(pipeline: VexRiscv): Unit = {
import pipeline.config._
import pipeline._
import Riscv._
val csrService = pipeline.service(classOf[CsrInterface])
val privilegeService = pipeline.service(classOf[PrivilegeService])
val core = pipeline plug new Area {
// Instantiate pmpaddr0 ... pmpaddr# CSRs.
for (i <- 0 until regions) {
if (i == 0) {
pmps += PmpRegister(null)
} else {
pmps += PmpRegister(pmps.last)
}
csrService.r(0x3b0 + i, pmps(i).state.addr)
csrService.w(0x3b0 + i, pmps(i).csr.addr)
}
// Instantiate pmpcfg0 ... pmpcfg# CSRs.
for (i <- 0 until (regions / 4)) {
csrService.r(0x3a0 + i,
31 -> pmps((i * 4) + 3).state.l, 23 -> pmps((i * 4) + 2).state.l,
15 -> pmps((i * 4) + 1).state.l, 7 -> pmps((i * 4) ).state.l,
27 -> pmps((i * 4) + 3).state.a, 26 -> pmps((i * 4) + 3).state.x,
25 -> pmps((i * 4) + 3).state.w, 24 -> pmps((i * 4) + 3).state.r,
19 -> pmps((i * 4) + 2).state.a, 18 -> pmps((i * 4) + 2).state.x,
17 -> pmps((i * 4) + 2).state.w, 16 -> pmps((i * 4) + 2).state.r,
11 -> pmps((i * 4) + 1).state.a, 10 -> pmps((i * 4) + 1).state.x,
9 -> pmps((i * 4) + 1).state.w, 8 -> pmps((i * 4) + 1).state.r,
3 -> pmps((i * 4) ).state.a, 2 -> pmps((i * 4) ).state.x,
1 -> pmps((i * 4) ).state.w, 0 -> pmps((i * 4) ).state.r
)
csrService.w(0x3a0 + i,
31 -> pmps((i * 4) + 3).csr.l, 23 -> pmps((i * 4) + 2).csr.l,
15 -> pmps((i * 4) + 1).csr.l, 7 -> pmps((i * 4) ).csr.l,
27 -> pmps((i * 4) + 3).csr.a, 26 -> pmps((i * 4) + 3).csr.x,
25 -> pmps((i * 4) + 3).csr.w, 24 -> pmps((i * 4) + 3).csr.r,
19 -> pmps((i * 4) + 2).csr.a, 18 -> pmps((i * 4) + 2).csr.x,
17 -> pmps((i * 4) + 2).csr.w, 16 -> pmps((i * 4) + 2).csr.r,
11 -> pmps((i * 4) + 1).csr.a, 10 -> pmps((i * 4) + 1).csr.x,
9 -> pmps((i * 4) + 1).csr.w, 8 -> pmps((i * 4) + 1).csr.r,
3 -> pmps((i * 4) ).csr.a, 2 -> pmps((i * 4) ).csr.x,
1 -> pmps((i * 4) ).csr.w, 0 -> pmps((i * 4) ).csr.r
)
}
// Connect memory ports to PMP logic.
val ports = for ((port, portId) <- portsInfo.zipWithIndex) yield new Area {
val address = port.bus.cmd(0).virtualAddress
port.bus.rsp.physicalAddress := address
// Only the first matching PMP region applies.
val hits = pmps.map(pmp => pmp.region.valid &
pmp.region.start <= address &
pmp.region.end > address &
(pmp.region.locked | ~privilegeService.isMachine()))
// M-mode has full access by default, others have none.
when(CountOne(hits) === 0) {
port.bus.rsp.allowRead := privilegeService.isMachine()
port.bus.rsp.allowWrite := privilegeService.isMachine()
port.bus.rsp.allowExecute := privilegeService.isMachine()
} otherwise {
port.bus.rsp.allowRead := MuxOH(OHMasking.first(hits), pmps.map(_.state.r))
port.bus.rsp.allowWrite := MuxOH(OHMasking.first(hits), pmps.map(_.state.w))
port.bus.rsp.allowExecute := MuxOH(OHMasking.first(hits), pmps.map(_.state.x))
}
port.bus.rsp.isIoAccess := ioRange(port.bus.rsp.physicalAddress)
port.bus.rsp.isPaging := False
port.bus.rsp.exception := False
port.bus.rsp.refilling := False
port.bus.busy := False
}
}
}
}

136
src/main/scala/vexriscv/plugin/VfuPlugin.scala Normal file
View File

@ -0,0 +1,136 @@
package vexriscv.plugin
import vexriscv.{DecoderService, ExceptionCause, ExceptionService, Stage, Stageable, VexRiscv}
import spinal.core._
import spinal.lib._
import spinal.lib.bus.bmb.WeakConnector
import spinal.lib.bus.misc.{AddressMapping, DefaultMapping}
import vexriscv.Riscv.IMM
object VfuPlugin{
val ROUND_MODE_WIDTH = 3
}
case class VfuParameter() //Empty for now
case class VfuCmd( p : VfuParameter ) extends Bundle{
val instruction = Bits(32 bits)
val inputs = Vec(Bits(32 bits), 2)
val rounding = Bits(VfuPlugin.ROUND_MODE_WIDTH bits)
}
case class VfuRsp(p : VfuParameter) extends Bundle{
val output = Bits(32 bits)
}
case class VfuBus(p : VfuParameter) extends Bundle with IMasterSlave{
val cmd = Stream(VfuCmd(p))
val rsp = Stream(VfuRsp(p))
def <<(m : VfuBus) : Unit = {
val s = this
s.cmd << m.cmd
m.rsp << s.rsp
}
override def asMaster(): Unit = {
master(cmd)
slave(rsp)
}
}
class VfuPlugin(val stageCount : Int,
val allowZeroLatency : Boolean,
val parameter : VfuParameter) extends Plugin[VexRiscv]{
def p = parameter
var bus : VfuBus = null
lazy val forkStage = pipeline.execute
lazy val joinStage = pipeline.stages(Math.min(pipeline.stages.length - 1, pipeline.indexOf(forkStage) + stageCount))
object VFU_ENABLE extends Stageable(Bool())
object VFU_IN_FLIGHT extends Stageable(Bool())
override def setup(pipeline: VexRiscv): Unit = {
import pipeline._
import pipeline.config._
bus = master(VfuBus(p))
val decoderService = pipeline.service(classOf[DecoderService])
decoderService.addDefault(VFU_ENABLE, False)
decoderService.add(
key = M"-------------------------0001011",
values = List(
VFU_ENABLE -> True,
REGFILE_WRITE_VALID -> True, //If you want to write something back into the integer register file
BYPASSABLE_EXECUTE_STAGE -> Bool(stageCount == 0),
BYPASSABLE_MEMORY_STAGE -> Bool(stageCount <= 1),
RS1_USE -> True,
RS2_USE -> True
)
)
}
override def build(pipeline: VexRiscv): Unit = {
import pipeline._
import pipeline.config._
val csr = pipeline plug new Area{
val factory = pipeline.service(classOf[CsrInterface])
val rounding = Reg(Bits(VfuPlugin.ROUND_MODE_WIDTH bits))
factory.rw(csrAddress = 0xBC0, bitOffset = 0, that = rounding)
}
forkStage plug new Area{
import forkStage._
val hazard = stages.dropWhile(_ != forkStage).tail.map(s => s.arbitration.isValid && s.input(HAS_SIDE_EFFECT)).orR
val scheduleWish = arbitration.isValid && input(VFU_ENABLE)
val schedule = scheduleWish && !hazard
arbitration.haltItself setWhen(scheduleWish && hazard)
val hold = RegInit(False) setWhen(schedule) clearWhen(bus.cmd.ready)
val fired = RegInit(False) setWhen(bus.cmd.fire) clearWhen(!arbitration.isStuckByOthers)
insert(VFU_IN_FLIGHT) := schedule || hold || fired
bus.cmd.valid := (schedule || hold) && !fired
arbitration.haltItself setWhen(bus.cmd.valid && !bus.cmd.ready)
bus.cmd.instruction := input(INSTRUCTION)
bus.cmd.inputs(0) := input(RS1)
bus.cmd.inputs(1) := input(RS2)
bus.cmd.rounding := csr.rounding
}
joinStage plug new Area{
import joinStage._
val rsp = if(forkStage != joinStage && allowZeroLatency) {
bus.rsp.s2mPipe()
} else {
bus.rsp.combStage()
}
rsp.ready := False
when(input(VFU_IN_FLIGHT) && input(REGFILE_WRITE_VALID)){
arbitration.haltItself setWhen(!bus.rsp.valid)
rsp.ready := !arbitration.isStuckByOthers
output(REGFILE_WRITE_DATA) := bus.rsp.output
}
}
pipeline.stages.drop(1).foreach(s => s.output(VFU_IN_FLIGHT) clearWhen(s.arbitration.isStuck))
addPrePopTask(() => stages.dropWhile(_ != memory).reverse.dropWhile(_ != joinStage).foreach(s => s.input(VFU_IN_FLIGHT).init(False)))
}
}

1
src/test/cpp/briey/main.cpp
View File

@ -6,7 +6,6 @@
#include "VBriey_RiscvCore.h"
#endif
#include "verilated.h"
#include "verilated_vcd_c.h"
#include <stdio.h>
#include <iostream>
#include <stdlib.h>

2
src/test/cpp/briey/makefile
View File

@ -13,7 +13,7 @@ ADDCFLAGS += -LDFLAGS -lSDL2
ifeq ($(TRACE),yes)
VERILATOR_ARGS += --trace
ADDCFLAGS += -CFLAGS -DTRACE
ADDCFLAGS += -CFLAGS -DTRACE --trace-fst
endif
ifeq ($(DEBUG),yes)
ADDCFLAGS += -CFLAGS "-g3 -O0"

38
src/test/cpp/briey/makefile~
View File

@ -1,38 +0,0 @@
DEBUG?=no
TRACE?=no
PRINT_PERF?=no
TRACE_START=0
ADDCFLAGS += -CFLAGS -pthread
ifeq ($(TRACE),yes)
VERILATOR_ARGS += --trace
ADDCFLAGS += -CFLAGS -DTRACE
endif
ifeq ($(DEBUG),yes)
ADDCFLAGS += -CFLAGS "-g3 -O0"
endif
ifneq ($(DEBUG),yes)
ADDCFLAGS += -CFLAGS "-O3"
endif
ifeq ($(PRINT_PERF),yes)
ADDCFLAGS += -CFLAGS -DPRINT_PERF
endif
ADDCFLAGS += -CFLAGS -DTRACE_START=${TRACE_START}
all: clean compile
run: compile
./obj_dir/VBriey
verilate:
verilator -cc ../../../../Briey.v -CFLAGS -std=c++11 ${ADDCFLAGS} --gdbbt ${VERILATOR_ARGS} -Wno-WIDTH --x-assign unique --exe main.cpp
compile: verilate
make -j -C obj_dir/ -f VBriey.mk VBriey
clean:
rm -rf obj_dir

7
src/test/cpp/common/framework.h
View File

@ -11,6 +11,7 @@
#include <iomanip>
#include <time.h>
#include <unistd.h>
#include "verilated_fst_c.h"
using namespace std;
@ -140,7 +141,7 @@ public:
string name;
uint64_t time = 0;
#ifdef TRACE
VerilatedVcdC* tfp;
VerilatedFstC* tfp;
#endif
ofstream logTraces;
@ -184,9 +185,9 @@ public:
// init trace dump
#ifdef TRACE
Verilated::traceEverOn(true);
tfp = new VerilatedVcdC;
tfp = new VerilatedFstC;
top->trace(tfp, 99);
tfp->open((string(name)+ ".vcd").c_str());
tfp->open((string(name)+ ".fst").c_str());
#endif
struct timespec start_time,tick_time;

2
src/test/cpp/murax/makefile
View File

@ -7,7 +7,7 @@ ADDCFLAGS += -CFLAGS -pthread -LDFLAGS -pthread
ifeq ($(TRACE),yes)
VERILATOR_ARGS += --trace
ADDCFLAGS += -CFLAGS -DTRACE
ADDCFLAGS += -CFLAGS -DTRACE --trace-fst
endif
ifeq ($(DEBUG),yes)
ADDCFLAGS += -CFLAGS "-g3 -O0"

181
src/test/cpp/raw/pmp/build/pmp.asm
View File

@ -22,21 +22,21 @@ Disassembly of section .crt_section:
80000024 <test0>:
80000024: 00000e13 li t3,0
80000028: 00000f17 auipc t5,0x0
8000002c: 340f0f13 addi t5,t5,832 # 80000368 <fail>
8000002c: 324f0f13 addi t5,t5,804 # 8000034c <fail>
80000030: 800000b7 lui ra,0x80000
80000034: 80008237 lui tp,0x80008
80000038: deadc137 lui sp,0xdeadc
8000003c: eef10113 addi sp,sp,-273 # deadbeef <pass+0x5eadbb7b>
80000040: 0020a023 sw sp,0(ra) # 80000000 <pass+0xfffffc8c>
80000044: 00222023 sw sp,0(tp) # 80008000 <pass+0x7c8c>
8000003c: eef10113 addi sp,sp,-273 # deadbeef <pass+0x5eadbb97>
80000040: 0020a023 sw sp,0(ra) # 80000000 <pass+0xfffffca8>
80000044: 00222023 sw sp,0(tp) # 80008000 <pass+0x7ca8>
80000048: 0000a183 lw gp,0(ra)
8000004c: 30311e63 bne sp,gp,80000368 <fail>
8000004c: 30311063 bne sp,gp,8000034c <fail>
80000050: 00022183 lw gp,0(tp) # 0 <_start-0x80000000>
80000054: 30311a63 bne sp,gp,80000368 <fail>
80000054: 2e311c63 bne sp,gp,8000034c <fail>
80000058: 071a02b7 lui t0,0x71a0
8000005c: 3a029073 csrw pmpcfg0,t0
80000060: 3a002373 csrr t1,pmpcfg0
80000064: 30629263 bne t0,t1,80000368 <fail>
80000064: 2e629463 bne t0,t1,8000034c <fail>
80000068: 1a1902b7 lui t0,0x1a190
8000006c: 30428293 addi t0,t0,772 # 1a190304 <_start-0x65e6fcfc>
80000070: 3a129073 csrw pmpcfg1,t0
@ -44,14 +44,14 @@ Disassembly of section .crt_section:
80000078: 90a28293 addi t0,t0,-1782 # f090a <_start-0x7ff0f6f6>
8000007c: 3a229073 csrw pmpcfg2,t0
80000080: 3a202373 csrr t1,pmpcfg2
80000084: 2e629263 bne t0,t1,80000368 <fail>
80000084: 2c629463 bne t0,t1,8000034c <fail>
80000088: 1c1e22b7 lui t0,0x1c1e2
8000008c: 90028293 addi t0,t0,-1792 # 1c1e1900 <_start-0x63e1e700>
80000090: 3a329073 csrw pmpcfg3,t0
80000094: 200002b7 lui t0,0x20000
80000098: 3b029073 csrw pmpaddr0,t0
8000009c: 3b002373 csrr t1,pmpaddr0
800000a0: 2c629463 bne t0,t1,80000368 <fail>
800000a0: 2a629663 bne t0,t1,8000034c <fail>
800000a4: fff00293 li t0,-1
800000a8: 3b129073 csrw pmpaddr1,t0
800000ac: 202002b7 lui t0,0x20200
@ -92,89 +92,89 @@ Disassembly of section .crt_section:
80000138: 0020a023 sw sp,0(ra)
8000013c: 00222023 sw sp,0(tp) # 0 <_start-0x80000000>
80000140: 0000a183 lw gp,0(ra)
80000144: 22311263 bne sp,gp,80000368 <fail>
80000144: 20311463 bne sp,gp,8000034c <fail>
80000148: 00000193 li gp,0
8000014c: 00022183 lw gp,0(tp) # 0 <_start-0x80000000>
80000150: 20311c63 bne sp,gp,80000368 <fail>
80000150: 1e311e63 bne sp,gp,8000034c <fail>
80000154 <test1>:
80000154: 00100e13 li t3,1
80000158: 00000f17 auipc t5,0x0
8000015c: 210f0f13 addi t5,t5,528 # 80000368 <fail>
8000015c: 1f4f0f13 addi t5,t5,500 # 8000034c <fail>
80000160: 079a12b7 lui t0,0x79a1
80000164: 80828293 addi t0,t0,-2040 # 79a0808 <_start-0x7865f7f8>
80000168: 3a029073 csrw pmpcfg0,t0
8000016c: 3a002373 csrr t1,pmpcfg0
80000170: 1e629c63 bne t0,t1,80000368 <fail>
80000170: 1c629e63 bne t0,t1,8000034c <fail>
80000174: 808000b7 lui ra,0x80800
80000178: deadc137 lui sp,0xdeadc
8000017c: eef10113 addi sp,sp,-273 # deadbeef <pass+0x5eadbb7b>
80000180: 0020a023 sw sp,0(ra) # 80800000 <pass+0x7ffc8c>
8000017c: eef10113 addi sp,sp,-273 # deadbeef <pass+0x5eadbb97>
80000180: 0020a023 sw sp,0(ra) # 80800000 <pass+0x7ffca8>
80000184: 00000f17 auipc t5,0x0
80000188: 010f0f13 addi t5,t5,16 # 80000194 <test2>
8000018c: 0000a183 lw gp,0(ra)
80000190: 1d80006f j 80000368 <fail>
80000190: 1bc0006f j 8000034c <fail>
80000194 <test2>:
80000194: 00200e13 li t3,2
80000198: 00000f17 auipc t5,0x0
8000019c: 1d0f0f13 addi t5,t5,464 # 80000368 <fail>
8000019c: 1b4f0f13 addi t5,t5,436 # 8000034c <fail>
800001a0: 071a02b7 lui t0,0x71a0
800001a4: 3a029073 csrw pmpcfg0,t0
800001a8: 3a002373 csrr t1,pmpcfg0
800001ac: 1a628e63 beq t0,t1,80000368 <fail>
800001ac: 1a628063 beq t0,t1,8000034c <fail>
800001b0: 3b305073 csrwi pmpaddr3,0
800001b4: 3b302373 csrr t1,pmpaddr3
800001b8: 1a031863 bnez t1,80000368 <fail>
800001b8: 18031a63 bnez t1,8000034c <fail>
800001bc: 3b205073 csrwi pmpaddr2,0
800001c0: 3b202373 csrr t1,pmpaddr2
800001c4: 1a030263 beqz t1,80000368 <fail>
800001c4: 18030463 beqz t1,8000034c <fail>
800001c8: 808000b7 lui ra,0x80800
800001cc: deadc137 lui sp,0xdeadc
800001d0: eef10113 addi sp,sp,-273 # deadbeef <pass+0x5eadbb7b>
800001d4: 0020a023 sw sp,0(ra) # 80800000 <pass+0x7ffc8c>
800001d0: eef10113 addi sp,sp,-273 # deadbeef <pass+0x5eadbb97>
800001d4: 0020a023 sw sp,0(ra) # 80800000 <pass+0x7ffca8>
800001d8: 00000f17 auipc t5,0x0
800001dc: 010f0f13 addi t5,t5,16 # 800001e8 <test3>
800001e0: 0000a183 lw gp,0(ra)
800001e4: 1840006f j 80000368 <fail>
800001e4: 1680006f j 8000034c <fail>
800001e8 <test3>:
800001e8: 00300e13 li t3,3
800001ec: 00000f17 auipc t5,0x0
800001f0: 17cf0f13 addi t5,t5,380 # 80000368 <fail>
800001f0: 160f0f13 addi t5,t5,352 # 8000034c <fail>
800001f4: 00ff02b7 lui t0,0xff0
800001f8: 3b32a073 csrs pmpaddr3,t0
800001fc: 3b302373 csrr t1,pmpaddr3
80000200: 16629463 bne t0,t1,80000368 <fail>
80000200: 14629663 bne t0,t1,8000034c <fail>
80000204: 0ff00293 li t0,255
80000208: 3b32a073 csrs pmpaddr3,t0
8000020c: 3b302373 csrr t1,pmpaddr3
80000210: 00ff02b7 lui t0,0xff0
80000214: 0ff28293 addi t0,t0,255 # ff00ff <_start-0x7f00ff01>
80000218: 14629863 bne t0,t1,80000368 <fail>
80000218: 12629a63 bne t0,t1,8000034c <fail>
8000021c: 00ff02b7 lui t0,0xff0
80000220: 3b32b073 csrc pmpaddr3,t0
80000224: 3b302373 csrr t1,pmpaddr3
80000228: 0ff00293 li t0,255
8000022c: 12629e63 bne t0,t1,80000368 <fail>
8000022c: 12629063 bne t0,t1,8000034c <fail>
80000230: 00ff02b7 lui t0,0xff0
80000234: 0ff28293 addi t0,t0,255 # ff00ff <_start-0x7f00ff01>
80000238: 3a02b073 csrc pmpcfg0,t0
8000023c: 3a002373 csrr t1,pmpcfg0
80000240: 079a02b7 lui t0,0x79a0
80000244: 12629263 bne t0,t1,80000368 <fail>
80000244: 10629463 bne t0,t1,8000034c <fail>
80000248: 00ff02b7 lui t0,0xff0
8000024c: 70728293 addi t0,t0,1799 # ff0707 <_start-0x7f00f8f9>
80000250: 3a02a073 csrs pmpcfg0,t0
80000254: 3a002373 csrr t1,pmpcfg0
80000258: 079a02b7 lui t0,0x79a0
8000025c: 70728293 addi t0,t0,1799 # 79a0707 <_start-0x7865f8f9>
80000260: 10629463 bne t0,t1,80000368 <fail>
80000260: 0e629663 bne t0,t1,8000034c <fail>
80000264 <test4>:
80000264: 00400e13 li t3,4
80000268: 00000f17 auipc t5,0x0
8000026c: 100f0f13 addi t5,t5,256 # 80000368 <fail>
8000026c: 0e4f0f13 addi t5,t5,228 # 8000034c <fail>
80000270: 00000117 auipc sp,0x0
80000274: 01010113 addi sp,sp,16 # 80000280 <test5>
80000278: 34111073 csrw mepc,sp
@ -183,83 +183,76 @@ Disassembly of section .crt_section:
80000280 <test5>:
80000280: 00500e13 li t3,5
80000284: 00000f17 auipc t5,0x0
80000288: 0e4f0f13 addi t5,t5,228 # 80000368 <fail>
80000288: 0c8f0f13 addi t5,t5,200 # 8000034c <fail>
8000028c: deadc137 lui sp,0xdeadc
80000290: eef10113 addi sp,sp,-273 # deadbeef <pass+0x5eadbb7b>
80000290: eef10113 addi sp,sp,-273 # deadbeef <pass+0x5eadbb97>
80000294: 808000b7 lui ra,0x80800
80000298: 0020a023 sw sp,0(ra) # 80800000 <pass+0x7ffc8c>
80000298: 0020a023 sw sp,0(ra) # 80800000 <pass+0x7ffca8>
8000029c: 00000f17 auipc t5,0x0
800002a0: 010f0f13 addi t5,t5,16 # 800002ac <test6>
800002a4: 0000a183 lw gp,0(ra)
800002a8: 0c00006f j 80000368 <fail>
800002a8: 0a40006f j 8000034c <fail>
800002ac <test6>:
800002ac: 00600e13 li t3,6
800002b0: 00000f17 auipc t5,0x0
800002b4: 0b8f0f13 addi t5,t5,184 # 80000368 <fail>
800002b8: deadc137 lui sp,0xdeadc
800002bc: eef10113 addi sp,sp,-273 # deadbeef <pass+0x5eadbb7b>
800002c0: 880000b7 lui ra,0x88000
800002c4: 0020a023 sw sp,0(ra) # 88000000 <pass+0x7fffc8c>
800002c8: 0000a183 lw gp,0(ra)
800002cc <test7>:
800002cc: 00700e13 li t3,7
800002d0: 00000f17 auipc t5,0x0
800002d4: 098f0f13 addi t5,t5,152 # 80000368 <fail>
800002d8: 890000b7 lui ra,0x89000
800002dc: ff008093 addi ra,ra,-16 # 88fffff0 <pass+0x8fffc7c>
800002e0: 0000a183 lw gp,0(ra)
800002e4: 00000f17 auipc t5,0x0
800002e8: 010f0f13 addi t5,t5,16 # 800002f4 <test8a>
800002ec: 0030a023 sw gp,0(ra)
800002f0: 0780006f j 80000368 <fail>
800002b0 <test7>:
800002b0: 00700e13 li t3,7
800002b4: 00000f17 auipc t5,0x0
800002b8: 098f0f13 addi t5,t5,152 # 8000034c <fail>
800002bc: 890000b7 lui ra,0x89000
800002c0: ff008093 addi ra,ra,-16 # 88fffff0 <pass+0x8fffc98>
800002c4: 0000a183 lw gp,0(ra)
800002c8: 00000f17 auipc t5,0x0
800002cc: 010f0f13 addi t5,t5,16 # 800002d8 <test8a>
800002d0: 0030a023 sw gp,0(ra)
800002d4: 0780006f j 8000034c <fail>
800002f4 <test8a>:
800002f4: 00800e13 li t3,8
800002f8: 00000f17 auipc t5,0x0
800002fc: 014f0f13 addi t5,t5,20 # 8000030c <test8b>
80000300: 00100493 li s1,1
80000304: 3a305073 csrwi pmpcfg3,0
80000308: 0600006f j 80000368 <fail>
800002d8 <test8a>:
800002d8: 00800e13 li t3,8
800002dc: 00000f17 auipc t5,0x0
800002e0: 014f0f13 addi t5,t5,20 # 800002f0 <test8b>
800002e4: 00100493 li s1,1
800002e8: 3a305073 csrwi pmpcfg3,0
800002ec: 0600006f j 8000034c <fail>
8000030c <test8b>:
8000030c: 00800e13 li t3,8
80000310: 1c1e22b7 lui t0,0x1c1e2
80000314: 90028293 addi t0,t0,-1792 # 1c1e1900 <_start-0x63e1e700>
80000318: 3a302373 csrr t1,pmpcfg3
8000031c: 04629663 bne t0,t1,80000368 <fail>
800002f0 <test8b>:
800002f0: 00800e13 li t3,8
800002f4: 1c1e22b7 lui t0,0x1c1e2
800002f8: 90028293 addi t0,t0,-1792 # 1c1e1900 <_start-0x63e1e700>
800002fc: 3a302373 csrr t1,pmpcfg3
80000300: 04629663 bne t0,t1,8000034c <fail>
80000320 <test9a>:
80000320: 00900e13 li t3,9
80000324: 00000f17 auipc t5,0x0
80000328: 044f0f13 addi t5,t5,68 # 80000368 <fail>
8000032c: 00000493 li s1,0
80000330: 00000117 auipc sp,0x0
80000334: 01010113 addi sp,sp,16 # 80000340 <test9b>
80000338: 34111073 csrw mepc,sp
8000033c: 30200073 mret
80000304 <test9a>:
80000304: 00900e13 li t3,9
80000308: 00000f17 auipc t5,0x0
8000030c: 044f0f13 addi t5,t5,68 # 8000034c <fail>
80000310: 00000493 li s1,0
80000314: 00000117 auipc sp,0x0
80000318: 01010113 addi sp,sp,16 # 80000324 <test9b>
8000031c: 34111073 csrw mepc,sp
80000320: 30200073 mret
80000340 <test9b>:
80000340: 00900e13 li t3,9
80000344: 00000f17 auipc t5,0x0
80000348: 014f0f13 addi t5,t5,20 # 80000358 <test9c>
8000034c: 00100493 li s1,1
80000350: 3ba05073 csrwi pmpaddr10,0
80000354: 0140006f j 80000368 <fail>
80000324 <test9b>:
80000324: 00900e13 li t3,9
80000328: 00000f17 auipc t5,0x0
8000032c: 014f0f13 addi t5,t5,20 # 8000033c <test9c>
80000330: 00100493 li s1,1
80000334: 3ba05073 csrwi pmpaddr10,0
80000338: 0140006f j 8000034c <fail>
80000358 <test9c>:
80000358: 00900e13 li t3,9
8000035c: fff00293 li t0,-1
80000360: 3ba02373 csrr t1,pmpaddr10
80000364: 00628863 beq t0,t1,80000374 <pass>
8000033c <test9c>:
8000033c: 00900e13 li t3,9
80000340: fff00293 li t0,-1
80000344: 3ba02373 csrr t1,pmpaddr10
80000348: 00628863 beq t0,t1,80000358 <pass>
80000368 <fail>:
80000368: f0100137 lui sp,0xf0100
8000036c: f2410113 addi sp,sp,-220 # f00fff24 <pass+0x700ffbb0>
80000370: 01c12023 sw t3,0(sp)
8000034c <fail>:
8000034c: f0100137 lui sp,0xf0100
80000350: f2410113 addi sp,sp,-220 # f00fff24 <pass+0x700ffbcc>
80000354: 01c12023 sw t3,0(sp)
80000374 <pass>:
80000374: f0100137 lui sp,0xf0100
80000378: f2010113 addi sp,sp,-224 # f00fff20 <pass+0x700ffbac>
8000037c: 00012023 sw zero,0(sp)
80000358 <pass>:
80000358: f0100137 lui sp,0xf0100
8000035c: f2010113 addi sp,sp,-224 # f00fff20 <pass+0x700ffbc8>
80000360: 00012023 sw zero,0(sp)

BIN
src/test/cpp/raw/pmp/build/pmp.elf
View File

Binary file not shown.

69
src/test/cpp/raw/pmp/build/pmp.hex
View File

@ -1,15 +1,15 @@
:0200000480007A
:10000000930400009700000093800001739050302B
:100010006F00400173101F3463940400730020309C
:1000200067000F00130E0000170F0000130F0F34AE
:1000200067000F00130E0000170F0000130F4F3270
:10003000B70000803782008037C1ADDE1301F1EEDA
:1000400023A020002320220083A10000631E313062
:1000500083210200631A3130B7021A077390023A03
:100060007323003A63926230B702191A93824230C6
:1000400023A020002320220083A100006310313070
:1000500083210200631C312EB7021A077390023A03
:100060007323003A6394622EB702191A93824230C6
:100070007390123AB7120F009382A2907390223AB3
:100080007323203A6392622EB7221E1C9382029041
:100080007323203A6394622CB7221E1C9382029041
:100090007390323AB70200207390023B7323003B07
:1000A0006394622C9302F0FF7390123BB7022020FE
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:1000B0007390223BB74200209382F2FF7390323B51
:1000C000B74200209382F2FF7390423BB742002078
:1000D0009382F2FF7390523BB70200239382F2FFA8
@ -19,41 +19,40 @@
:10011000930200007390C23B930200007390D23BA5
:10012000930200007390E23B9302F0FF7390F23B66
:100130003701C1001301E1FE23A02000232022008B
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:10015000631C3120130E1000170F0000130F0F2126
:1001400083A1000063143120930100008321020089
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:10016000B7129A07938282807390023A7323003AFF
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:100190006F00C01B130E2000170F0000130F4F1B22
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:1002200073B0323B7323303B9302F00F639E621234
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20
src/test/cpp/raw/pmp/build/pmp.map
View File

@ -8,26 +8,26 @@ onChipRam 0x0000000080000000 0x0000000000020000 w !xr
Linker script and memory map
LOAD build/src/crt.o
LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/8.3.0/rv32i/ilp32/libgcc.a
LOAD /opt/riscv_10092021/bin/../lib/gcc/riscv64-unknown-elf/8.3.0/rv32i/ilp32/libgcc.a
START GROUP
LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/8.3.0/../../../../riscv64-unknown-elf/lib/rv32i/ilp32/libc.a
LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/8.3.0/../../../../riscv64-unknown-elf/lib/rv32i/ilp32/libgloss.a
LOAD /opt/riscv_10092021/bin/../lib/gcc/riscv64-unknown-elf/8.3.0/../../../../riscv64-unknown-elf/lib/rv32i/ilp32/libc.a
LOAD /opt/riscv_10092021/bin/../lib/gcc/riscv64-unknown-elf/8.3.0/../../../../riscv64-unknown-elf/lib/rv32i/ilp32/libgloss.a
END GROUP
LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/8.3.0/rv32i/ilp32/libgcc.a
LOAD /opt/riscv_10092021/bin/../lib/gcc/riscv64-unknown-elf/8.3.0/rv32i/ilp32/libgcc.a
.crt_section 0x0000000080000000 0x380
.crt_section 0x0000000080000000 0x364
0x0000000080000000 . = ALIGN (0x4)
*crt.o(.text)
.text 0x0000000080000000 0x380 build/src/crt.o
.text 0x0000000080000000 0x364 build/src/crt.o
0x0000000080000000 _start
0x0000000080000014 trap
OUTPUT(build/pmp.elf elf32-littleriscv)
.data 0x0000000080000380 0x0
.data 0x0000000080000380 0x0 build/src/crt.o
.data 0x0000000080000364 0x0
.data 0x0000000080000364 0x0 build/src/crt.o
.bss 0x0000000080000380 0x0
.bss 0x0000000080000380 0x0 build/src/crt.o
.bss 0x0000000080000364 0x0
.bss 0x0000000080000364 0x0 build/src/crt.o
.riscv.attributes
0x0000000000000000 0x1a

10
src/test/cpp/raw/pmp/src/crt.S
View File

@ -206,11 +206,11 @@ test5:
// attempt to read/write overlapping regions from U-mode
test6:
li TEST_ID, 6
la TRAP_RETURN, fail
li x2, 0xdeadbeef
li x1, 0x88000000
sw x2, 0x0(x1) // should be OK (write region 6/7)
lw x3, 0x0(x1) // should be OK (write region 6/7)
//la TRAP_RETURN, fail
//li x2, 0xdeadbeef
//li x1, 0x88000000
//sw x2, 0x0(x1) // should be OK (write region 6/7)
//lw x3, 0x0(x1) // should be OK (write region 6/7)
test7:
li TEST_ID, 7