Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Fix DebugPlugin step by step

This commit is contained in:
Dolu1990 2020-04-07 12:13:40 +02:00
parent 31d2aaa05b
commit ddc59bc404
1 changed files with 3 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
src/main/scala/vexriscv/plugin/DebugPlugin.scala
View File

@ -213,18 +213,17 @@ class DebugPlugin(val debugClockDomain : ClockDomain, hardwareBreakpointCount :
iBusFetcher.haltIt() iBusFetcher.haltIt()
} }
when(stepIt) { when(stepIt && iBusFetcher.incoming()) {
//Assume nothing will stop the CPU in the decode stage iBusFetcher.haltIt()
when(decode.arbitration.isValid) { when(decode.arbitration.isValid) {
haltIt := True haltIt := True
decode.arbitration.flushNext := True
} }
} }
//Avoid having two C instruction executed in a single step //Avoid having two C instruction executed in a single step
if(pipeline(RVC_GEN)){ if(pipeline(RVC_GEN)){
val cleanStep = RegNext(stepIt && decode.arbitration.isFiring) init(False) val cleanStep = RegNext(stepIt && decode.arbitration.isFiring) init(False)
decode.arbitration.removeIt setWhen(cleanStep) execute.arbitration.flushNext setWhen(cleanStep)
} }
io.resetOut := RegNext(resetIt) io.resetOut := RegNext(resetIt)