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VexRiscv
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DataCache relax flush timings

This commit is contained in:
Dolu1990 2020-03-08 12:35:24 +01:00
parent 04bf1a4ced
commit defe3c5558
1 changed files with 5 additions and 3 deletions
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8
src/main/scala/vexriscv/ip/DataCache.scala
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@ -490,8 +490,7 @@ class DataCache(p : DataCacheConfig) extends Component{
//Evict the cache after reset logics //Evict the cache after reset logics
val flusher = new Area { val flusher = new Area {
val valid = RegInit(True) val valid = RegInit(False)
mmuRsp.physicalAddress init (0)
when(valid) { when(valid) {
tagsWriteCmd.valid := valid tagsWriteCmd.valid := valid
tagsWriteCmd.address := mmuRsp.physicalAddress(lineRange) tagsWriteCmd.address := mmuRsp.physicalAddress(lineRange)
@ -506,7 +505,10 @@ class DataCache(p : DataCacheConfig) extends Component{
} }
io.cpu.flush.ready := False io.cpu.flush.ready := False
when(io.cpu.flush.valid && !io.cpu.execute.isValid && !io.cpu.memory.isValid && !io.cpu.writeBack.isValid && !io.cpu.redo){ val start = RegInit(True) //Used to relax timings
start := !start && io.cpu.flush.valid && !io.cpu.execute.isValid && !io.cpu.memory.isValid && !io.cpu.writeBack.isValid && !io.cpu.redo
when(start){
io.cpu.flush.ready := True io.cpu.flush.ready := True
mmuRsp.physicalAddress.getDrivingReg(lineRange) := 0 mmuRsp.physicalAddress.getDrivingReg(lineRange) := 0
valid := True valid := True