Clear mprv on xretAwayFromMachine
This commit is contained in:
Dolu1990
parent
663174bc73
commit
e19e59b55c
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@ -2,6 +2,8 @@ package vexriscv.demo
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import spinal.core._
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import spinal.lib._
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import spinal.lib.com.jtag.Jtag
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import spinal.lib.cpu.riscv.debug.DebugTransportModuleParameter
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import spinal.lib.eda.bench._
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import spinal.lib.eda.icestorm.IcestormStdTargets
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import spinal.lib.eda.xilinx.VivadoFlow
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@ -9,7 +11,7 @@ import spinal.lib.io.InOutWrapper
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import vexriscv.demo.smp.VexRiscvSmpClusterGen
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import vexriscv.plugin.CsrAccess.{READ_ONLY, READ_WRITE, WRITE_ONLY}
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import vexriscv.{VexRiscv, VexRiscvConfig, plugin}
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import vexriscv.plugin.{BranchPlugin, CsrPlugin, CsrPluginConfig, DBusSimplePlugin, DecoderSimplePlugin, FullBarrelShifterPlugin, HazardSimplePlugin, IBusSimplePlugin, IntAluPlugin, LightShifterPlugin, NONE, RegFilePlugin, SrcPlugin, YamlPlugin}
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import vexriscv.plugin.{BranchPlugin, CsrPlugin, CsrPluginConfig, DBusSimplePlugin, DebugPlugin, DecoderSimplePlugin, EmbeddedRiscvJtag, FullBarrelShifterPlugin, HazardSimplePlugin, IBusSimplePlugin, IntAluPlugin, LightShifterPlugin, NONE, Plugin, RegFilePlugin, SrcPlugin, YamlPlugin}
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import scala.collection.mutable.ArrayBuffer
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import scala.util.Random
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@ -409,88 +411,94 @@ object VexRiscvCustomSynthesisBench {
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def main(args: Array[String]) {
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def gen(csr : CsrPlugin) = new VexRiscv(
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config = VexRiscvConfig(
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plugins = List(
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new IBusSimplePlugin(
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resetVector = 0x80000000l,
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cmdForkOnSecondStage = false,
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cmdForkPersistence = false,
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prediction = NONE,
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catchAccessFault = false,
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compressedGen = false
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),
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new DBusSimplePlugin(
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catchAddressMisaligned = false,
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catchAccessFault = false
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),
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new DecoderSimplePlugin(
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catchIllegalInstruction = false
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),
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new RegFilePlugin(
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regFileReadyKind = plugin.SYNC,
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zeroBoot = false
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),
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new IntAluPlugin,
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new SrcPlugin(
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separatedAddSub = false,
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executeInsertion = true
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),
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csr,
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new FullBarrelShifterPlugin(),
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new HazardSimplePlugin(
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bypassExecute = true,
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bypassMemory = true,
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bypassWriteBack = true,
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bypassWriteBackBuffer = true,
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pessimisticUseSrc = false,
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pessimisticWriteRegFile = false,
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pessimisticAddressMatch = false
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),
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new BranchPlugin(
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earlyBranch = false,
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catchAddressMisaligned = false
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),
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new YamlPlugin("cpu0.yaml")
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def gen(csr : CsrPlugin, p : Plugin[VexRiscv]) = {
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val cpu = new VexRiscv(
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config = VexRiscvConfig(
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plugins = List(
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p,
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new IBusSimplePlugin(
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resetVector = 0x80000000l,
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cmdForkOnSecondStage = false,
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cmdForkPersistence = false,
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prediction = NONE,
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catchAccessFault = false,
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compressedGen = false
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),
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new DBusSimplePlugin(
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catchAddressMisaligned = false,
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catchAccessFault = false
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),
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new DecoderSimplePlugin(
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catchIllegalInstruction = false
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),
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new RegFilePlugin(
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regFileReadyKind = plugin.SYNC,
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zeroBoot = false
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),
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new IntAluPlugin,
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new SrcPlugin(
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separatedAddSub = false,
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executeInsertion = true
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),
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csr,
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new FullBarrelShifterPlugin(),
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new HazardSimplePlugin(
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bypassExecute = true,
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bypassMemory = true,
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bypassWriteBack = true,
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bypassWriteBackBuffer = true,
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pessimisticUseSrc = false,
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pessimisticWriteRegFile = false,
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pessimisticAddressMatch = false
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),
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new BranchPlugin(
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earlyBranch = false,
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catchAddressMisaligned = false
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),
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new YamlPlugin("cpu0.yaml")
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)
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)
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)
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)
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val fixedMtvec = new Rtl {
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override def getName(): String = "Fixed MTVEC"
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override def getRtlPath(): String = "fixedMtvec.v"
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SpinalVerilog(gen(new CsrPlugin(CsrPluginConfig.smallest(0x80000000l))).setDefinitionName(getRtlPath().split("\\.").head))
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}
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val writeOnlyMtvec = new Rtl {
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override def getName(): String = "write only MTVEC"
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override def getRtlPath(): String = "woMtvec.v"
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SpinalVerilog(gen(new CsrPlugin(CsrPluginConfig.smallest(null).copy(mtvecAccess = WRITE_ONLY))).setDefinitionName(getRtlPath().split("\\.").head))
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}
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val readWriteMtvec = new Rtl {
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override def getName(): String = "read write MTVEC"
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override def getRtlPath(): String = "wrMtvec.v"
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SpinalVerilog(gen(new CsrPlugin(CsrPluginConfig.smallest(null).copy(mtvecAccess = READ_WRITE))).setDefinitionName(getRtlPath().split("\\.").head))
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}
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val fixedMtvecRoCounter = new Rtl {
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override def getName(): String = "Fixed MTVEC, read only mcycle/minstret"
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override def getRtlPath(): String = "fixedMtvecRoCounter.v"
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SpinalVerilog(gen(new CsrPlugin(CsrPluginConfig.smallest(0x80000000l).copy(mcycleAccess = READ_ONLY, minstretAccess = READ_ONLY))).setDefinitionName(getRtlPath().split("\\.").head))
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cpu.rework {
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for (plugin <- cpu.config.plugins) plugin match {
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case plugin: DebugPlugin => plugin.debugClockDomain {
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plugin.io.bus.setAsDirectionLess()
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val jtag = slave(new Jtag())
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.setName("jtag")
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jtag <> plugin.io.bus.fromJtag()
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}
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case _ =>
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}
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}
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cpu
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}
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val rwMtvecRoCounter = new Rtl {
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override def getName(): String = "read write MTVEC, read only mcycle/minstret"
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override def getRtlPath(): String = "readWriteMtvecRoCounter.v"
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SpinalVerilog(gen(new CsrPlugin(CsrPluginConfig.smallest(null).copy(mtvecAccess = READ_WRITE, mcycleAccess = READ_ONLY, minstretAccess = READ_ONLY))).setDefinitionName(getRtlPath().split("\\.").head))
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val riscvDebug = new Rtl {
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override def getName(): String = "riscvDebug"
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override def getRtlPath(): String = "riscvDebug.v"
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SpinalVerilog(gen(new CsrPlugin(CsrPluginConfig.smallest(0x80000000l).copy(withPrivilegedDebug = true)), new EmbeddedRiscvJtag(
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p = DebugTransportModuleParameter(
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addressWidth = 7,
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version = 1,
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idle = 7
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),
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withTunneling = false,
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withTap = true
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)).setDefinitionName(getRtlPath().split("\\.").head))
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}
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val vexDebug = new Rtl {
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override def getName(): String = "vexDebug"
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override def getRtlPath(): String = "vexDebug.v"
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SpinalVerilog(gen(new CsrPlugin(CsrPluginConfig.smallest(0x80000000l)),
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new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset")))
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).setDefinitionName(getRtlPath().split("\\.").head))
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}
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// val rtls = List(twoStage, twoStageBarell, twoStageMulDiv, twoStageAll, smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache, fullNoMmuNoCache, noCacheNoMmuMaxPerf, fullNoMmuMaxPerf, fullNoMmu, full, linuxBalanced, linuxBalancedSmp)
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val rtls = List(fixedMtvec, writeOnlyMtvec, readWriteMtvec,fixedMtvecRoCounter, rwMtvecRoCounter)
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val rtls = List(riscvDebug, vexDebug)
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// val rtls = List(smallest)
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val targets = XilinxStdTargets() ++ AlteraStdTargets() ++ IcestormStdTargets().take(1)
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@ -470,6 +470,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
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var externalMhartId : UInt = null
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var utime : UInt = null
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var stoptime : Bool = null
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var xretAwayFromMachine : Bool = null
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var debugBus : DebugHartBus = null
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var debugMode : Bool = null
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@ -633,6 +634,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
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decoderService.add(SFENCE_VMA, List(IS_SFENCE_VMA -> True))
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}
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xretAwayFromMachine = False
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injectionPort = withPrivilegedDebug generate pipeline.service(classOf[IBusFetcher]).getInjectionPort()
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debugMode = withPrivilegedDebug generate Bool().setName("debugMode")
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@ -751,7 +753,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
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val prv = RegInit(U"11")
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val step = RegInit(False) //TODO
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val nmip = False
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val mprven = False
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val mprven = True
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val cause = RegInit(U"000")
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val stoptime = RegInit(False)
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val stopcount = RegInit(False)
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@ -1380,14 +1382,20 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
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mstatus.MIE := mstatus.MPIE
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mstatus.MPIE := True
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jumpInterface.payload := mepc
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if(privilegeGen) privilegeReg := mstatus.MPP
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if(privilegeGen) {
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privilegeReg := mstatus.MPP
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xretAwayFromMachine setWhen(mstatus.MPP < 3)
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}
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}
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if(supervisorGen) is(1){
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sstatus.SPP := U"0"
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sstatus.SIE := sstatus.SPIE
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sstatus.SPIE := True
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jumpInterface.payload := sepc
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if(privilegeGen) privilegeReg := U"0" @@ sstatus.SPP
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if(privilegeGen) {
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privilegeReg := U"0" @@ sstatus.SPP
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xretAwayFromMachine := True
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}
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}
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}
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}
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@ -69,7 +69,7 @@ class MmuPlugin(ioRange : UInt => Bool,
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import pipeline._
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import pipeline.config._
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import Riscv._
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val csrService = pipeline.service(classOf[CsrInterface])
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val csrService = pipeline.service(classOf[CsrPlugin])
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//Sorted by priority
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val sortedPortsInfo = portsInfo.sortBy(_.priority)
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@ -89,6 +89,7 @@ class MmuPlugin(ioRange : UInt => Bool,
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val csr = pipeline plug new Area{
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val status = new Area{
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val sum, mxr, mprv = RegInit(False)
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mprv clearWhen(csrService.xretAwayFromMachine)
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}
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val satp = new Area {
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val mode = RegInit(False)
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