exception code can now be bigger than 4 bits
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646911a373
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e1e1be5797
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@ -26,13 +26,20 @@ trait DecoderService{
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def addDefault(key : Stageable[_ <: BaseType], value : Any)
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def addDefault(key : Stageable[_ <: BaseType], value : Any)
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}
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}
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case class ExceptionCause() extends Bundle{
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case class ExceptionCause(codeWidth : Int) extends Bundle{
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val code = UInt(4 bits)
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val code = UInt(codeWidth bits)
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val badAddr = UInt(32 bits)
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val badAddr = UInt(32 bits)
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def resizeCode(width : Int): ExceptionCause ={
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val ret = ExceptionCause(width)
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ret.badAddr := badAddr
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ret.code := code.resized
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ret
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}
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}
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}
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trait ExceptionService{
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trait ExceptionService{
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def newExceptionPort(stage : Stage, priority : Int = 0) : Flow[ExceptionCause]
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def newExceptionPort(stage : Stage, priority : Int = 0, codeWidth : Int = 4) : Flow[ExceptionCause]
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def isExceptionPending(stage : Stage) : Bool
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def isExceptionPending(stage : Stage) : Bool
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}
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}
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@ -34,7 +34,7 @@ object CsrAccess {
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case class ExceptionPortInfo(port : Flow[ExceptionCause],stage : Stage, priority : Int)
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case class ExceptionPortInfo(port : Flow[ExceptionCause],stage : Stage, priority : Int, codeWidth : Int)
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case class CsrPluginConfig(
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case class CsrPluginConfig(
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catchIllegalAccess : Boolean,
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catchIllegalAccess : Boolean,
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mvendorid : BigInt,
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mvendorid : BigInt,
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@ -441,9 +441,9 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
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//Mannage ExceptionService calls
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//Mannage ExceptionService calls
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val exceptionPortsInfos = ArrayBuffer[ExceptionPortInfo]()
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val exceptionPortsInfos = ArrayBuffer[ExceptionPortInfo]()
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override def newExceptionPort(stage : Stage, priority : Int = 0) = {
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override def newExceptionPort(stage : Stage, priority : Int = 0, codeWidth : Int = 4) = {
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val interface = Flow(ExceptionCause())
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val interface = Flow(ExceptionCause(codeWidth))
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exceptionPortsInfos += ExceptionPortInfo(interface,stage,priority)
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exceptionPortsInfos += ExceptionPortInfo(interface,stage,priority,codeWidth)
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interface
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interface
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}
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}
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@ -847,10 +847,11 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
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//Aggregate all exception port and remove required instructions
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//Aggregate all exception port and remove required instructions
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val exceptionPortCtrl = exceptionPortsInfos.nonEmpty generate new Area{
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val exceptionPortCtrl = exceptionPortsInfos.nonEmpty generate new Area{
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val codeWidth = exceptionPortsInfos.map(_.codeWidth).max
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val firstStageIndexWithExceptionPort = exceptionPortsInfos.map(i => indexOf(i.stage)).min
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val firstStageIndexWithExceptionPort = exceptionPortsInfos.map(i => indexOf(i.stage)).min
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val exceptionValids = Vec(stages.map(s => Bool().setPartialName(s.getName())))
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val exceptionValids = Vec(stages.map(s => Bool().setPartialName(s.getName())))
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val exceptionValidsRegs = Vec(stages.map(s => Reg(Bool).init(False).setPartialName(s.getName()))).allowUnsetRegToAvoidLatch
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val exceptionValidsRegs = Vec(stages.map(s => Reg(Bool).init(False).setPartialName(s.getName()))).allowUnsetRegToAvoidLatch
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val exceptionContext = Reg(ExceptionCause())
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val exceptionContext = Reg(ExceptionCause(codeWidth))
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val exceptionTargetPrivilegeUncapped = U"11"
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val exceptionTargetPrivilegeUncapped = U"11"
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switch(exceptionContext.code){
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switch(exceptionContext.code){
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@ -876,17 +877,19 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
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val groupedByStage = exceptionPortsInfos.map(_.stage).distinct.map(s => {
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val groupedByStage = exceptionPortsInfos.map(_.stage).distinct.map(s => {
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val stagePortsInfos = exceptionPortsInfos.filter(_.stage == s).sortWith(_.priority > _.priority)
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val stagePortsInfos = exceptionPortsInfos.filter(_.stage == s).sortWith(_.priority > _.priority)
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val stagePort = stagePortsInfos.length match{
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val stagePort = stagePortsInfos.length match{
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case 1 => stagePortsInfos.head.port
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case 1 => {
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stagePortsInfos.head.port.translateWith(stagePortsInfos.head.port.payload.resizeCode(codeWidth))
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}
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case _ => {
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case _ => {
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val groupedPort = Flow(ExceptionCause())
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val groupedPort = Flow(ExceptionCause(codeWidth))
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val valids = stagePortsInfos.map(_.port.valid)
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val valids = stagePortsInfos.map(_.port.valid)
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val codes = stagePortsInfos.map(_.port.payload)
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val codes = stagePortsInfos.map(_.port.payload.resizeCode(codeWidth))
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groupedPort.valid := valids.orR
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groupedPort.valid := valids.orR
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groupedPort.payload := MuxOH(OHMasking.first(stagePortsInfos.map(_.port.valid).asBits), codes)
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groupedPort.payload := MuxOH(OHMasking.first(stagePortsInfos.map(_.port.valid).asBits), codes)
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groupedPort
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groupedPort
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}
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}
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}
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}
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ExceptionPortInfo(stagePort,s,0)
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ExceptionPortInfo(stagePort,s,0, codeWidth)
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})
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})
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val sortedByStage = groupedByStage.sortWith((a, b) => pipeline.indexOf(a.stage) < pipeline.indexOf(b.stage))
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val sortedByStage = groupedByStage.sortWith((a, b) => pipeline.indexOf(a.stage) < pipeline.indexOf(b.stage))
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@ -16,9 +16,9 @@ class HaltOnExceptionPlugin() extends Plugin[VexRiscv] with ExceptionService {
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//Mannage ExceptionService calls
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//Mannage ExceptionService calls
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val exceptionPortsInfos = ArrayBuffer[ExceptionPortInfo]()
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val exceptionPortsInfos = ArrayBuffer[ExceptionPortInfo]()
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def exceptionCodeWidth = 4
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def exceptionCodeWidth = 4
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override def newExceptionPort(stage : Stage, priority : Int = 0) = {
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override def newExceptionPort(stage : Stage, priority : Int = 0, codeWidth : Int = 4) = {
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val interface = Flow(ExceptionCause())
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val interface = Flow(ExceptionCause(4))
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exceptionPortsInfos += ExceptionPortInfo(interface,stage,priority)
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exceptionPortsInfos += ExceptionPortInfo(interface,stage,priority, codeWidth)
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interface
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interface
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}
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}
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override def isExceptionPending(stage : Stage): Bool = False
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override def isExceptionPending(stage : Stage): Bool = False
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