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litex add hardwarebreapoint parameter

This commit is contained in:
Dolu1990 2023-09-20 09:08:18 +02:00
parent acf6ad3bfd
commit e21dc6cda5
2 changed files with 8 additions and 3 deletions
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4
src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
View File

@ -32,7 +32,8 @@ case class VexRiscvSmpClusterParameter(cpuConfigs : Seq[VexRiscvConfig],
forcePeripheralWidth : Boolean = true, forcePeripheralWidth : Boolean = true,
outOfOrderDecoder : Boolean = true, outOfOrderDecoder : Boolean = true,
fpu : Boolean = false, fpu : Boolean = false,
privilegedDebug : Boolean = false) privilegedDebug : Boolean = false,
hardwareBreakpoints : Int = 0)
class VexRiscvSmpClusterBase(p : VexRiscvSmpClusterParameter) extends Area with PostInitCallback{ class VexRiscvSmpClusterBase(p : VexRiscvSmpClusterParameter) extends Area with PostInitCallback{
val cpuCount = p.cpuConfigs.size val cpuCount = p.cpuConfigs.size
@ -85,6 +86,7 @@ class VexRiscvSmpClusterBase(p : VexRiscvSmpClusterParameter) extends Area with
cpu.dBus -> List(dBusCoherent.bmb) cpu.dBus -> List(dBusCoherent.bmb)
) )
cpu.hardwareBreakpointCount.load(p.hardwareBreakpoints)
if(!p.privilegedDebug) { if(!p.privilegedDebug) {
cpu.enableDebugBmb( cpu.enableDebugBmb(
debugCd = debugCd.outputClockDomain, debugCd = debugCd.outputClockDomain,

7
src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala
View File

@ -114,6 +114,7 @@ object VexRiscvLitexSmpClusterCmdGen extends App {
var iCacheWays = 2 var iCacheWays = 2
var dCacheWays = 2 var dCacheWays = 2
var privilegedDebug = false var privilegedDebug = false
var hardwareBreakpoints = 0
var liteDramWidth = 128 var liteDramWidth = 128
var coherentDma = false var coherentDma = false
var wishboneMemory = false var wishboneMemory = false
@ -130,7 +131,7 @@ object VexRiscvLitexSmpClusterCmdGen extends App {
var exposeTime = false var exposeTime = false
assert(new scopt.OptionParser[Unit]("VexRiscvLitexSmpClusterCmdGen") { assert(new scopt.OptionParser[Unit]("VexRiscvLitexSmpClusterCmdGen") {
help("help").text("prints this usage text") help("help").text("prints this usage text")
opt[Unit]("coherent-dma") action { (v, c) => coherentDma = true } opt[Unit] ("coherent-dma") action { (v, c) => coherentDma = true }
opt[String]("cpu-count") action { (v, c) => cpuCount = v.toInt } opt[String]("cpu-count") action { (v, c) => cpuCount = v.toInt }
opt[String]("ibus-width") action { (v, c) => iBusWidth = v.toInt } opt[String]("ibus-width") action { (v, c) => iBusWidth = v.toInt }
opt[String]("dbus-width") action { (v, c) => dBusWidth = v.toInt } opt[String]("dbus-width") action { (v, c) => dBusWidth = v.toInt }
@ -139,6 +140,7 @@ object VexRiscvLitexSmpClusterCmdGen extends App {
opt[String]("icache-ways") action { (v, c) => iCacheWays = v.toInt } opt[String]("icache-ways") action { (v, c) => iCacheWays = v.toInt }
opt[String]("dcache-ways") action { (v, c) => dCacheWays = v.toInt } opt[String]("dcache-ways") action { (v, c) => dCacheWays = v.toInt }
opt[Boolean]("privileged-debug") action { (v, c) => privilegedDebug = v } opt[Boolean]("privileged-debug") action { (v, c) => privilegedDebug = v }
opt[Int] ("hardware-breakpoints") action { (v, c) => hardwareBreakpoints = v }
opt[String]("litedram-width") action { (v, c) => liteDramWidth = v.toInt } opt[String]("litedram-width") action { (v, c) => liteDramWidth = v.toInt }
opt[String]("netlist-directory") action { (v, c) => netlistDirectory = v } opt[String]("netlist-directory") action { (v, c) => netlistDirectory = v }
opt[String]("netlist-name") action { (v, c) => netlistName = v } opt[String]("netlist-name") action { (v, c) => netlistName = v }
@ -189,7 +191,8 @@ object VexRiscvLitexSmpClusterCmdGen extends App {
outOfOrderDecoder = outOfOrderDecoder, outOfOrderDecoder = outOfOrderDecoder,
fpu = fpu, fpu = fpu,
jtagHeaderIgnoreWidth = 0, jtagHeaderIgnoreWidth = 0,
privilegedDebug = privilegedDebug privilegedDebug = privilegedDebug,
hardwareBreakpoints = hardwareBreakpoints
), ),
liteDram = LiteDramNativeParameter(addressWidth = 32, dataWidth = liteDramWidth), liteDram = LiteDramNativeParameter(addressWidth = 32, dataWidth = liteDramWidth),
liteDramMapping = SizeMapping(0x40000000l, 0x40000000l), liteDramMapping = SizeMapping(0x40000000l, 0x40000000l),