Add decoder bench

sim/cmd.txt

@@ -1,4 +0,0 @@
-
-
-verilator -cc  ../VexRiscv.v --trace -Wno-WIDTH --exe tester.cpp
-make -j -C obj_dir/ -f VVexRiscv.mk VVexRiscv

sim/tester.cpp

@@ -1,40 +0,0 @@
-#include "VVexRiscv.h"
-#include "verilated.h"
-#include "verilated_vcd_c.h"
-#include <stdio.h>
-
-int main(int argc, char **argv, char **env) {
-  int i;
-  int clk;
-  printf("start\n");
-  Verilated::commandArgs(argc, argv);
-  // init top verilog instance
-  VVexRiscv* top = new VVexRiscv;
-  // init trace dump
-  Verilated::traceEverOn(true);
-  VerilatedVcdC* tfp = new VerilatedVcdC;
-  top->trace (tfp, 99);
-  tfp->open ("sim.vcd");
-  // initialize simulation inputs
-  top->clk = 1;
- // top->rst = 1;
- // top->cen = 0;
- // top->wen = 0;
- // top->dat = 0x55;
-  // run simulation for 100 clock periods
-  for (i=0; i<20; i++) {
- //   top->rst = (i < 2);
-    // dump variables into VCD file and toggle clock
-    for (clk=0; clk<2; clk++) {
-      tfp->dump (2*i+clk);
-      top->clk = !top->clk;
-      top->eval ();
-    }
-  //  top->cen = (i > 5);
-  //  top->wen = (i == 10);
-    if (Verilated::gotFinish())  exit(0);
-  }
-  tfp->close();
-  printf("done\n");
-  exit(0);
-}

src/main/scala/SpinalRiscv/TopLevel.scala

@@ -151,6 +151,11 @@ trait DecoderService{
   def addDefault(key : Stageable[_ <: Data], value : Any)
 }
 
+
+case class Node(val value : BigInt,val careAbout : BigInt){
+
+}
+
 class DecoderSimplePlugin extends Plugin[VexRiscv] with DecoderService {
   override def add(encoding: Seq[(MaskedLiteral, Seq[(Stageable[_ <: Data], Any)])]): Unit = encoding.foreach(e => this.add(e._1,e._2))
   override def add(key: MaskedLiteral, values: Seq[(Stageable[_ <: Data], Any)]): Unit = {
@@ -177,6 +182,9 @@ class DecoderSimplePlugin extends Plugin[VexRiscv] with DecoderService {
     import pipeline.config._
 
     val stageables = encodings.flatMap(_._2.map(_._1)).toSet
+
+    
+
     stageables.foreach(e => if(defaults.contains(e.asInstanceOf[Stageable[Data]]))
       insert(e.asInstanceOf[Stageable[Data]]) := defaults(e.asInstanceOf[Stageable[Data]])
     else
@@ -194,6 +202,17 @@ class DecoderSimplePlugin extends Plugin[VexRiscv] with DecoderService {
       }
     }
   }
+
+  def bench(toplevel : VexRiscv): Unit ={
+    toplevel.rework{
+      import toplevel.config._
+      toplevel.getAllIo.toList.foreach(_.asDirectionLess())
+      toplevel.decode.input(INSTRUCTION) := Delay((in Bits(32 bits)).setName("instruction"),2)
+      val stageables = encodings.flatMap(_._2.map(_._1)).toSet
+      stageables.foreach(e => out(Delay(toplevel.decode.insert(e),2)).setName(e.getName))
+      toplevel.getAdditionalNodesRoot.clear()
+    }
+  }
 }
 
 class NoPredictionBranchPlugin extends Plugin[VexRiscv]{
@@ -817,13 +836,13 @@ class FullBarrielShifterPlugin extends Plugin[VexRiscv]{
 
 object TopLevel {
   def main(args: Array[String]) {
-    SpinalVerilog{
+    SpinalVerilog {
       val config = VexRiscvConfig(
         pcWidth = 32
       )
 
       config.plugins ++= List(
-        new PcManagerSimplePlugin(0,true),
+        new PcManagerSimplePlugin(0, true),
         new IBusSimplePlugin,
         new DecoderSimplePlugin,
         new RegFilePlugin(SYNC),
@@ -831,16 +850,15 @@ object TopLevel {
         new SrcPlugin,
         new FullBarrielShifterPlugin,
         new DBusSimplePlugin,
-//        new HazardSimplePlugin(true,true,true,true),
-        new HazardSimplePlugin(false,false,false,false),
+        //        new HazardSimplePlugin(true,true,true,true),
+        new HazardSimplePlugin(false, false, false, false),
         new NoPredictionBranchPlugin
-//        new OutputAluResult
+        //        new OutputAluResult
       )
 
       val toplevel = new VexRiscv(config)
 
-//      val iBus = toplevel.service(classOf[IBusSimplePlugin])
-//      val dBus = toplevel.service(classOf[DBusSimplePlugin])
+//      toplevel.service(classOf[DecoderSimplePlugin]).bench(toplevel)
 
 
       toplevel

src/test/cpp/testA/main.cpp

@@ -93,7 +93,7 @@ int main(int argc, char **argv, char **env) {
 	int clk;
 	int error = 0;
 	printf("start\n");
-	loadHex("testA.hex");
+	loadHex("../../hex/testA.hex");
 	Verilated::commandArgs(argc, argv);
 	// init top verilog instance
 	VVexRiscv* top = new VVexRiscv;