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VexRiscv
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fiber update

This commit is contained in:
Dolu1990 2021-03-05 22:04:20 +01:00
parent 0530d22a1d
commit e384bfe145
4 changed files with 27 additions and 17 deletions
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15
src/main/scala/vexriscv/VexRiscvBmbGenerator.scala
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@ -7,7 +7,7 @@ import spinal.lib.com.jtag.{Jtag, JtagTapInstructionCtrl}
import spinal.lib.generator._
import spinal.lib.slave
import vexriscv.plugin._
import spinal.core.fiber._
object VexRiscvBmbGenerator{
val DEBUG_NONE = 0
@ -34,7 +34,7 @@ case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGener
val timerInterrupt = product[Bool]
val softwareInterrupt = product[Bool]
def setTimerInterrupt(that: Handle[Bool]) = Dependable(that, timerInterrupt){timerInterrupt := that}
def setTimerInterrupt(that: Handle[Bool]) = Dependable(that, timerInterrupt){timerInterrupt := that}
def setSoftwareInterrupt(that: Handle[Bool]) = Dependable(that, softwareInterrupt){softwareInterrupt := that}
@ -45,14 +45,14 @@ case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGener
def enableJtag(debugCd : ClockDomainResetGenerator, resetCd : ClockDomainResetGenerator) : Unit = debugCd{
this.debugClockDomain.merge(debugCd.outputClockDomain)
val resetBridge = resetCd.asyncReset(debugReset, ResetSensitivity.HIGH)
debugAskReset.load(null)
debugAskReset.loadNothing()
withDebug.load(DEBUG_JTAG)
}
def enableJtagInstructionCtrl(debugCd : ClockDomainResetGenerator, resetCd : ClockDomainResetGenerator) : Unit = debugCd{
this.debugClockDomain.merge(debugCd.outputClockDomain)
val resetBridge = resetCd.asyncReset(debugReset, ResetSensitivity.HIGH)
debugAskReset.load(null)
debugAskReset.loadNothing()
withDebug.load(DEBUG_JTAG_CTRL)
dependencies += jtagClockDomain
}
@ -60,7 +60,7 @@ case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGener
def enableDebugBus(debugCd : ClockDomainResetGenerator, resetCd : ClockDomainResetGenerator) : Unit = debugCd{
this.debugClockDomain.merge(debugCd.outputClockDomain)
val resetBridge = resetCd.asyncReset(debugReset, ResetSensitivity.HIGH)
debugAskReset.load(null)
debugAskReset.loadNothing()
withDebug.load(DEBUG_BUS)
}
@ -69,16 +69,15 @@ case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGener
def enableDebugBmb(debugCd : ClockDomainResetGenerator, resetCd : ClockDomainResetGenerator, mapping : AddressMapping)(implicit debugMaster : BmbImplicitDebugDecoder = null) : Unit = debugCd{
this.debugClockDomain.merge(debugCd.outputClockDomain)
val resetBridge = resetCd.asyncReset(debugReset, ResetSensitivity.HIGH)
debugAskReset.load(null)
debugAskReset.loadNothing()
withDebug.load(DEBUG_BMB)
val slaveModel = interconnectSmp.addSlave(
val slaveModel = debugCd.outputClockDomain on interconnectSmp.addSlave(
accessSource = debugBmbAccessSource,
accessCapabilities = debugBmbAccessSource.derivate(DebugExtensionBus.getBmbAccessParameter(_)),
accessRequirements = debugBmbAccessRequirements,
bus = debugBmb,
mapping = mapping
)
slaveModel.onClockDomain(debugCd.outputClockDomain)
debugBmb.derivatedFrom(debugBmbAccessRequirements)(Bmb(_))
if(debugMaster != null) interconnectSmp.addConnection(debugMaster.bus, debugBmb)
dependencies += debugBmb

3
src/main/scala/vexriscv/demo/smp/Misc.scala
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@ -2,6 +2,7 @@ package vexriscv.demo.smp
import spinal.core._
import spinal.core.fiber._
import spinal.lib.bus.bmb._
import spinal.lib.bus.wishbone.{Wishbone, WishboneConfig, WishboneSlaveFactory}
import spinal.lib.com.jtag.Jtag
@ -9,7 +10,7 @@ import spinal.lib._
import spinal.lib.bus.bmb.sim.{BmbMemoryMultiPort, BmbMemoryTester}
import spinal.lib.bus.misc.{AddressMapping, DefaultMapping, SizeMapping}
import spinal.lib.eda.bench.Bench
import spinal.lib.generator.{Generator, Handle}
import spinal.lib.generator._
import spinal.lib.misc.Clint
import spinal.lib.sim.{SimData, SparseMemory, StreamDriver, StreamMonitor, StreamReadyRandomizer}
import vexriscv.{VexRiscv, VexRiscvConfig}

15
src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
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@ -11,7 +11,9 @@ import spinal.lib.bus.wishbone.{Wishbone, WishboneConfig, WishboneToBmb, Wishbon
import spinal.lib.com.jtag.{Jtag, JtagInstructionDebuggerGenerator, JtagTapInstructionCtrl}
import spinal.lib.com.jtag.sim.JtagTcp
import spinal.lib.com.jtag.xilinx.Bscane2BmbMasterGenerator
import spinal.lib.generator.Handle
import spinal.lib.generator._
import spinal.core.fiber._
import spinal.idslplugin.PostInitCallback
import spinal.lib.misc.plic.PlicMapping
import spinal.lib.system.debugger.SystemDebuggerConfig
import vexriscv.ip.{DataCacheAck, DataCacheConfig, DataCacheMemBus, InstructionCache, InstructionCacheConfig}
@ -25,7 +27,7 @@ import vexriscv.ip.fpu.FpuParameter
case class VexRiscvSmpClusterParameter(cpuConfigs : Seq[VexRiscvConfig], withExclusiveAndInvalidation : Boolean, forcePeripheralWidth : Boolean = true, outOfOrderDecoder : Boolean = true)
class VexRiscvSmpClusterBase(p : VexRiscvSmpClusterParameter) extends Generator{
class VexRiscvSmpClusterBase(p : VexRiscvSmpClusterParameter) extends Generator with PostInitCallback{
val cpuCount = p.cpuConfigs.size
val debugCd = ClockDomainResetGenerator()
@ -36,11 +38,16 @@ class VexRiscvSmpClusterBase(p : VexRiscvSmpClusterParameter) extends Generator{
systemCd.holdDuration.load(63)
systemCd.setInput(debugCd)
this.onClockDomain(systemCd.outputClockDomain)
systemCd.outputClockDomain.push()
override def postInitCallback(): VexRiscvSmpClusterBase.this.type = {
systemCd.outputClockDomain.pop()
this
}
implicit val interconnect = BmbInterconnectGenerator()
val debugBridge = JtagInstructionDebuggerGenerator() onClockDomain(debugCd.outputClockDomain)
val debugBridge = debugCd.outputClockDomain on JtagInstructionDebuggerGenerator()
debugBridge.jtagClockDomain.load(ClockDomain.external("jtag", withReset = false))
val debugPort = debugBridge.produceIo(debugBridge.logic.jtagBridge.io.ctrl)

11
src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala
View File

@ -1,9 +1,11 @@
package vexriscv.demo.smp
import spinal.core._
import spinal.core.fiber._
import spinal.lib.bus.bmb._
import spinal.lib.bus.misc.{AddressMapping, DefaultMapping, SizeMapping}
import spinal.lib.bus.wishbone.{WishboneConfig, WishboneToBmbGenerator}
import spinal.lib.generator.GeneratorComponent
import spinal.lib.sim.SparseMemory
import vexriscv.demo.smp.VexRiscvSmpClusterGen.vexRiscvConfig
import vexriscv.plugin.{AesPlugin, DBusCachedPlugin}
@ -126,9 +128,9 @@ object VexRiscvLitexSmpClusterCmdGen extends App {
)
def dutGen = {
val toplevel = new VexRiscvLitexSmpCluster(
val toplevel = GeneratorComponent(new VexRiscvLitexSmpCluster(
p = parameter
).toComponent()
))
toplevel
}
@ -197,9 +199,10 @@ object VexRiscvLitexSmpClusterOpenSbi extends App{
)
def dutGen = {
val top = new VexRiscvLitexSmpCluster(
import GeneratorComponent.toGenerator
val top = new GeneratorComponent(new VexRiscvLitexSmpCluster(
p = parameter
).toComponent()
))
top.rework{
top.clintWishbone.setAsDirectionLess.allowDirectionLessIo
top.peripheral.setAsDirectionLess.allowDirectionLessIo.simPublic()