#60 Added automated linux regression in travis
Fix DBusCached plugin access sharing for the MMU deadlock when exception is in the decode stage Fix IBusSimplePlugin issues with used with non regular configs + MMU Bring back the LinuxGen config into a light one
This commit is contained in:
Charles Papon
parent
2810ff05b0
commit
e47b76fa67
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@ -0,0 +1,3 @@
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[submodule "src/test/resources/VexRiscvRegressionData"]
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path = src/test/resources/VexRiscvRegressionData
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url = ../VexRiscvRegressionData.git
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15
.travis.yml
15
.travis.yml
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@ -11,8 +11,8 @@ scala:
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sbt_args: -no-colors -J-Xss2m
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script:
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- export VEXRISCV_REGRESSION_CONFIG_COUNT=100
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- export VEXRISCV_REGRESSION_FREERTOS_COUNT=no
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- export VEXRISCV_REGRESSION_THREAD_COUNT=1
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- sbt -jvm-opts travis/jvmopts.compile compile
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- sbt -jvm-opts travis/jvmopts.test test
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@ -22,7 +22,11 @@ jdk:
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# - openjdk7
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env:
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- secure: "v7FHP8yK/zixpv1ML05qcRhZfDVDFdTmTPjfMZHL7gmrJveVDgze22x4tY4tB1+JEXhKuVTYvimOrX/Ok+rOOT5gVKLowv4PUQwCR+HgWVIbqjcfZNLsa369v03/p4K/zbjJSiXFahZYOXa0ApED2KWHcVfCrNsPv0UF7YZGiIa1Q/lPBwfmpN1rLih2Mpgn4KVaJky22t7JXJyVrNdGVmIA51slVbyFwFAE8Ww/0tkC+i2PUcWWRMIxtXP4iyq/9Npcq5VdqOatKfWHqAElLfKSPNMYLMlcyxyNpNx4paq8cL6fQxFcBLi9M2msz2i/qpKv30a0tzNo5bQQgucAXOQJB2Buks728upLuqsr+k25hwcqrtjyMOr9UQkt7qXAJH/0kimW7aW1yoMxbm/6mNG98X9D1EzNRewHAKatwJeFy1bw5qIuSQxPBwQMGloManrHOHGotmHKk7Y+dgM/z1UlaAdxSQuKWGXBc8QlQvif8puPYEdJMoInJNRxiWfYu06XnmzTXgMketK7RdULM9DVYzw8hzS2EIWKu8Oa0zn0PTevD2YeJNd4G8mDqO0vz5hloIc7pFsq/exQUB/kFozfCsnvhW8P+MPN0LpuSpptBQTsLWbM5BH0hd46HoWcneDdlMvVrUcgsTPmmSroIkLIEUo+Y2iN5eQHPPp85Cw="
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- VEXRISCV_REGRESSION_CONFIG_COUNT=0
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- VEXRISCV_REGRESSION_CONFIG_COUNT=5
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- VEXRISCV_REGRESSION_CONFIG_COUNT=5
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- VEXRISCV_REGRESSION_CONFIG_COUNT=5
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- VEXRISCV_REGRESSION_CONFIG_COUNT=5
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before_install:
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# JDK fix
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@ -34,11 +38,9 @@ before_install:
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# Verilator
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- sudo apt-get install git make autoconf g++ flex bison -y # First time prerequisites
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- git clone http://git.veripool.org/git/verilator # Only first time
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- unset VERILATOR_ROOT # For bash
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- wget https://www.veripool.org/ftp/verilator-4.012.tgz
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- tar xvzf verilator*.t*gz
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- cd verilator
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- git pull # Make sure we're up-to-date
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- git checkout verilator_3_916
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- autoconf # Create ./configure script
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- ./configure
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- make -j$(nproc)
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@ -48,6 +50,7 @@ before_install:
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- git clone https://github.com/SpinalHDL/SpinalHDL.git -b dev
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- cd VexRiscv
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- git submodule update --init --recursive
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#- curl -T README.md -udolu1990:$BINTRAY_KEY https://api.bintray.com/content/spinalhdl/VexRiscv/test/0.0.4/README.md
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#- curl -X POST -udolu1990:$BINTRAY_KEY https://api.bintray.com/content/spinalhdl/VexRiscv/test/0.0.4/publish
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#- sbt compile
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@ -33,7 +33,7 @@ case class ExceptionCause() extends Bundle{
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trait ExceptionService{
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def newExceptionPort(stage : Stage, priority : Int = 0) : Flow[ExceptionCause]
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def isExceptionPending() : Bool
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def isExceptionPending(stage : Stage) : Bool
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}
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trait PrivilegeService{
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@ -40,13 +40,13 @@ cd VexRiscv
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Run regressions =>
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sbt "runMain vexriscv.demo.LinuxGen -r"
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cd src/test/cpp/regression
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make run IBUS=CACHED DBUS=CACHED DEBUG_PLUGIN=STD DHRYSTONE=yes SUPERVISOR=yes CSR=yes COMPRESSED=no LRSC=yes AMO=yes REDO=10 TRACE=no
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make clean run IBUS=CACHED DBUS=CACHED DEBUG_PLUGIN=STD DHRYSTONE=yes SUPERVISOR=yes MMU=yes CSR=yes COMPRESSED=no MUL=yes DIV=yes LRSC=yes AMO=yes REDO=10 TRACE=no COREMARK=yes LINUX_REGRESSION=yes
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Run linux in simulation (Require the machime mode emulator compiled in SIM mode) =>
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sbt "runMain vexriscv.demo.LinuxGen"
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cd src/test/cpp/regression
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export BUILDROOT=/home/miaou/pro/riscv/buildrootSpinal
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make run IBUS=CACHED DBUS=CACHED DEBUG_PLUGIN=STD SUPERVISOR=yes CSR=yes COMPRESSED=no LRSC=yes AMO=yes REDO=0 DHRYSTONE=no LINUX_SOC=yes EMULATOR=../../../main/c/emulator/build/emulator.bin VMLINUX=$BUILDROOT/output/images/Image DTB=$BUILDROOT/board/spinal/vexriscv_sim/rv32.dtb RAMDISK=$BUILDROOT/output/images/rootfs.cpio TRACE=no FLOW_INFO=no
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make clean run IBUS=CACHED DBUS=CACHED DEBUG_PLUGIN=STD SUPERVISOR=yes CSR=yes COMPRESSED=no LRSC=yes AMO=yes REDO=0 DHRYSTONE=no LINUX_SOC=yes EMULATOR=../../../main/c/emulator/build/emulator.bin VMLINUX=$BUILDROOT/output/images/Image DTB=$BUILDROOT/board/spinal/vexriscv_sim/rv32.dtb RAMDISK=$BUILDROOT/output/images/rootfs.cpio WITH_USER_IO=yes TRACE=no FLOW_INFO=no
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Run linux with QEMU (Require the machime mode emulator compiled in QEMU mode)
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export BUILDROOT=/home/miaou/pro/riscv/buildrootSpinal
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@ -94,10 +94,12 @@ rm VexRiscv.v
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cp $DATA/VexRiscv.v ../../../..
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make run IBUS=CACHED DBUS=CACHED DEBUG_PLUGIN=STD SUPERVISOR=yes CSR=yes COMPRESSED=no LRSC=yes AMO=yes REDO=0 DHRYSTONE=no LINUX_SOC=yes EMULATOR=$DATA/emulator.bin VMLINUX=$DATA/vmlinux.bin DTB=$DATA/rv32.dtb RAMDISK=$DATA/rootfs.cpio TRACE=no FLOW_INFO=no
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make clean run IBUS=CACHED DBUS=CACHED DEBUG_PLUGIN=STD DHRYSTONE=no SUPERVISOR=yes CSR=yes COMPRESSED=no MUL=yes DIV=yes LRSC=yes AMO=yes MMU=yes REDO=1 TRACE=no LINUX_REGRESSION=yes
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qemu-system-riscv32 -nographic -machine virt -m 1536M -device loader,file=$DATA/emulator.bin,addr=0x80000000,cpu-num=0 -device loader,file=$DATA/rv32.dtb,addr=0xC3000000 -device loader,file=$DATA/vmlinux.bin,addr=0xC0000000 -device loader,file=$DATA/rootfs.cpio,addr=0xc2000000
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make run IBUS=CACHED DBUS=CACHED DEBUG_PLUGIN=STD DHRYSTONE=yess SUPERVISOR=yes CSR=yes COMPRESSED=yes MUL=yes DIV=yes LRSC=yes AMO=yes REDO=1 TRACE=no LINUX_REGRESSION=yes
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program ../../../main/c/emulator/build/emulator.bin 0x80000000 verify
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soc.loadBin(EMULATOR, 0x80000000);
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@ -149,12 +151,12 @@ object LinuxGen {
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new IBusCachedPlugin(
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resetVector = 0x80000000l,
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compressedGen = false,
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prediction = DYNAMIC_TARGET,
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prediction = NONE,
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injectorStage = false,
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config = InstructionCacheConfig(
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cacheSize = 4096*4,
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cacheSize = 4096*1,
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bytePerLine = 32,
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wayCount = 4,
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wayCount = 1,
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addressWidth = 32,
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cpuDataWidth = 32,
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memDataWidth = 32,
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@ -184,9 +186,9 @@ object LinuxGen {
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dBusCmdSlavePipe = true,
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dBusRspSlavePipe = true,
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config = new DataCacheConfig(
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cacheSize = 4096*4,
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cacheSize = 4096*1,
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bytePerLine = 32,
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wayCount = 4,
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wayCount = 1,
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addressWidth = 32,
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cpuDataWidth = 32,
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memDataWidth = 32,
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@ -163,3 +163,8 @@ class MuraxApb3Timer extends Component{
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interruptCtrl.io.inputs(1) := timerB.io.full
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io.interrupt := interruptCtrl.io.pendings.orR
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}
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object MuraxApb3TimerGen extends App{
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SpinalVhdl(new MuraxApb3Timer())
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}
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@ -327,8 +327,8 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception
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interface
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}
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var exceptionPending : Bool = null
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override def isExceptionPending(): Bool = exceptionPending
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var exceptionPendings : Vec[Bool] = null
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override def isExceptionPending(stage : Stage): Bool = exceptionPendings(pipeline.stages.indexOf(stage))
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var jumpInterface : Flow[UInt] = null
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var timerInterrupt, externalInterrupt, softwareInterrupt : Bool = null
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@ -420,7 +420,7 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception
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jumpInterface.valid := False
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jumpInterface.payload.assignDontCare()
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exceptionPending = False
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exceptionPendings = Vec(Bool, pipeline.stages.length)
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timerInterrupt = in Bool() setName("timerInterrupt")
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externalInterrupt = in Bool() setName("externalInterrupt")
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softwareInterrupt = in Bool() setName("softwareInterrupt") default(False)
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@ -721,7 +721,7 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception
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//Avoid the PC register of the last stage to change durring an exception handleing (Used to fill Xepc)
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stages.last.dontSample.getOrElseUpdate(PC, ArrayBuffer[Bool]()) += exceptionValids.last
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exceptionPending setWhen(exceptionValidsRegs.orR)
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exceptionPendings := exceptionValidsRegs
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} else null
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@ -292,7 +292,8 @@ class DBusCachedPlugin(config : DataCacheConfig,
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val forceDatapath = False
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when(dBusAccess.cmd.valid){
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decode.arbitration.haltByOther := True
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when(!stagesFromExecute.map(_.arbitration.isValid).orR && !pipeline.service(classOf[ExceptionService]).isExceptionPending()){
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val exceptionService = pipeline.service(classOf[ExceptionService])
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when(!stagesFromExecute.map(s => s.arbitration.isValid || exceptionService.isExceptionPending(s)).orR){
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when(!cache.io.cpu.redo) {
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cache.io.cpu.execute.isValid := True
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dBusAccess.cmd.ready := !execute.arbitration.isStuck
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@ -66,8 +66,8 @@ class DecoderSimplePlugin(catchIllegalInstruction : Boolean = false, forceLegalI
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}
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}
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val defaults = mutable.HashMap[Stageable[_ <: BaseType], BaseType]()
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val encodings = mutable.HashMap[MaskedLiteral,ArrayBuffer[(Stageable[_ <: BaseType], BaseType)]]()
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val defaults = mutable.LinkedHashMap[Stageable[_ <: BaseType], BaseType]()
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val encodings = mutable.LinkedHashMap[MaskedLiteral,ArrayBuffer[(Stageable[_ <: BaseType], BaseType)]]()
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var decodeExceptionPort : Flow[ExceptionCause] = null
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@ -105,7 +105,7 @@ class DecoderSimplePlugin(catchIllegalInstruction : Boolean = false, forceLegalI
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} else {
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var offset = 0
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var defaultValue, defaultCare = BigInt(0)
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val offsetOf = mutable.HashMap[Stageable[_ <: BaseType], Int]()
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val offsetOf = mutable.LinkedHashMap[Stageable[_ <: BaseType], Int]()
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//Build defaults value and field offset map
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stageables.foreach(e => {
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@ -191,8 +191,8 @@ object DecodingBench extends App{
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object Symplify{
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val cache = mutable.HashMap[Bits,mutable.HashMap[Masked,Bool]]()
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def getCache(addr : Bits) = cache.getOrElseUpdate(addr,mutable.HashMap[Masked,Bool]())
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val cache = mutable.LinkedHashMap[Bits,mutable.LinkedHashMap[Masked,Bool]]()
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def getCache(addr : Bits) = cache.getOrElseUpdate(addr,mutable.LinkedHashMap[Masked,Bool]())
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//Generate terms logic for the given input
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def logicOf(input : Bits,terms : Seq[Masked]) = terms.map(t => getCache(input).getOrElseUpdate(t,t === input)).asBits.orR
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@ -21,7 +21,7 @@ class HaltOnExceptionPlugin() extends Plugin[VexRiscv] with ExceptionService {
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exceptionPortsInfos += ExceptionPortInfo(interface,stage,priority)
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interface
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}
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override def isExceptionPending(): Bool = False
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override def isExceptionPending(stage : Stage): Bool = False
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override def build(pipeline: VexRiscv): Unit = {
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@ -220,17 +220,18 @@ class IBusSimplePlugin(resetVector : BigInt,
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pipeline plug new FetchArea(pipeline) {
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var cmd = Stream(IBusSimpleCmd())
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iBus.cmd << (if(cmdForkPersistence && !cmdForkOnSecondStage) cmd.s2mPipe() else cmd)
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val cmdWithS2mPipe = cmdForkPersistence && (!cmdForkOnSecondStage || mmuBus != null)
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iBus.cmd << (if(cmdWithS2mPipe) cmd.s2mPipe() else cmd)
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//Avoid sending to many iBus cmd
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val pendingCmd = Reg(UInt(log2Up(pendingMax + 1) bits)) init (0)
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val pendingCmdNext = pendingCmd + cmd.fire.asUInt - iBus.rsp.fire.asUInt
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pendingCmd := pendingCmdNext
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def cmdForkStage = if(!cmdForkPersistence || !cmdForkOnSecondStage) iBusRsp.stages(if(cmdForkOnSecondStage) 1 else 0) else iBusRsp.stages(1)
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val secondStagePersistence = cmdForkPersistence && cmdForkOnSecondStage && !cmdWithS2mPipe
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def cmdForkStage = if(!secondStagePersistence) iBusRsp.stages(if(cmdForkOnSecondStage) 1 else 0) else iBusRsp.stages(1)
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val cmdFork = if(!cmdForkPersistence || !cmdForkOnSecondStage) new Area {
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val cmdFork = if(!secondStagePersistence) new Area {
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//This implementation keep the cmd on the bus until it's executed or the the pipeline is flushed
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def stage = cmdForkStage
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stage.halt setWhen(stage.input.valid && (!cmd.valid || !cmd.ready))
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@ -255,7 +256,7 @@ class IBusSimplePlugin(resetVector : BigInt,
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mmuBus.cmd.isValid := cmdForkStage.input.valid
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mmuBus.cmd.virtualAddress := cmdForkStage.input.payload
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mmuBus.cmd.bypassTranslation := False
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mmuBus.end := !cmdForkStage.output.fire || flush
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mmuBus.end := cmdForkStage.output.fire || flush
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cmd.pc := mmuBus.rsp.physicalAddress(31 downto 2) @@ "00"
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@ -265,7 +266,10 @@ class IBusSimplePlugin(resetVector : BigInt,
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cmd.valid := False
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}
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cmdForkStage.halt.setWhen(mmuBus.busy)
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when(mmuBus.busy){
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cmdForkStage.input.valid := False
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cmdForkStage.input.ready := False
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}
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val joinCtx = stageXToIBusRsp(cmdForkStage, mmuBus.rsp)
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}
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@ -280,7 +284,7 @@ class IBusSimplePlugin(resetVector : BigInt,
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val discardCounter = Reg(UInt(log2Up(pendingMax + 1) bits)) init (0)
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discardCounter := discardCounter - (iBus.rsp.fire && discardCounter =/= 0).asUInt
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when(flush) {
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if(cmdForkOnSecondStage && cmdForkPersistence)
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if(secondStagePersistence)
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discardCounter := pendingCmd + cmd.valid.asUInt - iBus.rsp.fire.asUInt
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else
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discardCounter := (if(cmdForkOnSecondStage) pendingCmdNext else pendingCmd - iBus.rsp.fire.asUInt)
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@ -318,7 +322,7 @@ class IBusSimplePlugin(resetVector : BigInt,
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if(memoryTranslatorPortConfig != null){
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redoRequired setWhen( stages.last.input.valid && mmu.joinCtx.refilling)
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redoBranch.valid := redoRequired && iBusRsp.readyForError
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redoBranch.payload := stages.last.input.payload
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redoBranch.payload := decode.input(PC)
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decode.arbitration.flushAll setWhen(redoBranch.valid)
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}
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@ -149,8 +149,6 @@ class MmuPlugin(ioRange : UInt => Bool,
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}
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val shared = new Area {
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val busy = Reg(Bool) init(False)
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val State = new SpinalEnum{
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val IDLE, L1_CMD, L1_RSP, L0_CMD, L0_RSP = newElement()
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}
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@ -182,7 +180,6 @@ class MmuPlugin(ioRange : UInt => Bool,
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is(State.IDLE){
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for(port <- portsInfo.sortBy(_.priority)){
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when(port.bus.cmd.isValid && port.bus.rsp.refilling){
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busy := True
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vpn(1) := port.bus.cmd.virtualAddress(31 downto 22)
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vpn(0) := port.bus.cmd.virtualAddress(21 downto 12)
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portId := port.id
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@ -1634,6 +1634,7 @@ public:
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cout << "FAIL " << name << " at PC=" << hex << setw(8) << top->VexRiscv->writeBack_PC << dec; //<< " seed : " << seed <<
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if(riscvRefEnable) cout << hex << " REF PC=" << riscvRef.lastPc << " REF I=" << riscvRef.lastInstruction << dec;
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cout << " time=" << i;
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cout << endl;
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cycles += instanceCycles;
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@ -3059,29 +3060,22 @@ public:
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//#endif
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#include <unistd.h>
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#include <termios.h>
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#include <fcntl.h>
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termios stdinRestoreSettings;
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void stdinNonBuffered(){
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static struct termios old, new1;
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tcgetattr(STDIN_FILENO, &old); /* grab old terminal i/o settings */
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new1 = old; /* make new settings same as old settings */
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new1.c_lflag &= ~ICANON; /* disable buffered i/o */
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tcgetattr(STDIN_FILENO, &old); // grab old terminal i/o settings
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new1 = old; // make new settings same as old settings
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new1.c_lflag &= ~ICANON; // disable buffered i/o
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new1.c_lflag &= ~ECHO;
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tcsetattr(STDIN_FILENO, TCSANOW, &new1); /* use these new terminal i/o settings now */
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tcsetattr(STDIN_FILENO, TCSANOW, &new1); // use these new terminal i/o settings now
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setvbuf(stdin, NULL, _IONBF, 0);
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stdinRestoreSettings = old;
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}
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||||
|
||||
void stdoutNonBuffered(){
|
||||
setvbuf(stdout, NULL, _IONBF, 0);
|
||||
}
|
||||
|
||||
void stdinRestore(){
|
||||
tcsetattr(STDIN_FILENO, TCSANOW, &stdinRestoreSettings); /* use these new terminal i/o settings now */
|
||||
}
|
||||
|
||||
bool stdinNonEmpty(){
|
||||
struct timeval tv;
|
||||
|
|
@ -3094,6 +3088,17 @@ bool stdinNonEmpty(){
|
|||
return (FD_ISSET(0, &fds));
|
||||
}
|
||||
|
||||
|
||||
void stdoutNonBuffered(){
|
||||
setvbuf(stdout, NULL, _IONBF, 0);
|
||||
}
|
||||
|
||||
void stdinRestore(){
|
||||
tcsetattr(STDIN_FILENO, TCSANOW, &stdinRestoreSettings);
|
||||
}
|
||||
|
||||
|
||||
|
||||
void my_handler(int s){
|
||||
printf("Caught signal %d\n",s);
|
||||
stdinRestore();
|
||||
|
|
@ -3111,23 +3116,39 @@ void captureCtrlC(){
|
|||
sigaction(SIGINT, &sigIntHandler, NULL);
|
||||
}
|
||||
|
||||
#ifdef LINUX_SOC
|
||||
|
||||
|
||||
|
||||
#if defined(LINUX_SOC) || defined(LINUX_REGRESSION)
|
||||
#include <queue>
|
||||
class LinuxSoc : public Workspace{
|
||||
public:
|
||||
queue <char> customCin;
|
||||
void pushCin(string m){
|
||||
for(char& c : m) {
|
||||
customCin.push(c);
|
||||
}
|
||||
}
|
||||
|
||||
LinuxSoc(string name) : Workspace(name) {
|
||||
#ifdef WITH_USER_IO
|
||||
stdinNonBuffered();
|
||||
stdoutNonBuffered();
|
||||
captureCtrlC();
|
||||
#endif
|
||||
stdoutNonBuffered();
|
||||
}
|
||||
|
||||
virtual ~LinuxSoc(){
|
||||
#ifdef WITH_USER_IO
|
||||
stdinRestore();
|
||||
#endif
|
||||
}
|
||||
virtual bool isDBusCheckedRegion(uint32_t address){ return true;}
|
||||
virtual bool isPerifRegion(uint32_t addr) { return (addr & 0xF0000000) == 0xF0000000 || (addr & 0xE0000000) == 0xE0000000;}
|
||||
virtual bool isMmuRegion(uint32_t addr) { return true; }
|
||||
|
||||
|
||||
|
||||
virtual void dBusAccess(uint32_t addr,bool wr, uint32_t size,uint32_t mask, uint32_t *data, bool *error) {
|
||||
if(isPerifRegion(addr)) switch(addr){
|
||||
//TODO Emulate peripherals here
|
||||
|
|
@ -3137,18 +3158,24 @@ public:
|
|||
case 0xFFFFFFEC: if(wr) mTimeCmp = (mTimeCmp & 0x00000000FFFFFFFF) | (((uint64_t)*data) << 32); else *data = mTimeCmp >> 32; break;
|
||||
case 0xFFFFFFF8:
|
||||
if(wr){
|
||||
cout << (char)*data;
|
||||
logTraces << (char)*data;
|
||||
char c = (char)*data;
|
||||
cout << c;
|
||||
logTraces << c;
|
||||
logTraces.flush();
|
||||
onStdout(c);
|
||||
} else {
|
||||
#ifdef WITH_USER_IO
|
||||
if(stdinNonEmpty()){
|
||||
char c;
|
||||
read(0, &c, 1);
|
||||
*data = c;
|
||||
//cout << "getchar " << c << endl;
|
||||
} else
|
||||
#endif
|
||||
if(!customCin.empty()){
|
||||
*data = customCin.front();
|
||||
customCin.pop();
|
||||
} else {
|
||||
*data = -1;
|
||||
//cout << "getchar NONE" << endl;
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
|
@ -3158,7 +3185,43 @@ public:
|
|||
|
||||
Workspace::dBusAccess(addr,wr,size,mask,data,error);
|
||||
}
|
||||
|
||||
virtual void onStdout(char c){
|
||||
|
||||
}
|
||||
};
|
||||
|
||||
|
||||
class LinuxRegression: public LinuxSoc{
|
||||
public:
|
||||
string pendingLine = "";
|
||||
bool pendingLineContain(string m) {
|
||||
return strstr(pendingLine.c_str(), m.c_str()) != NULL;
|
||||
}
|
||||
|
||||
enum State{LOGIN, ECHO_FILE, HEXDUMP, HEXDUMP_CHECK, PASS};
|
||||
State state = LOGIN;
|
||||
LinuxRegression(string name) : LinuxSoc(name) {
|
||||
|
||||
}
|
||||
|
||||
~LinuxRegression() {
|
||||
}
|
||||
|
||||
|
||||
virtual void onStdout(char c){
|
||||
pendingLine += c;
|
||||
switch(state){
|
||||
case LOGIN: if (pendingLineContain("buildroot login:")) { pushCin("root\n"); state = ECHO_FILE; } break;
|
||||
case ECHO_FILE: if (pendingLineContain("# ")) { pushCin("echo \"miaou\" > test.txt\n"); state = HEXDUMP; pendingLine = "";} break;
|
||||
case HEXDUMP: if (pendingLineContain("# ")) { pushCin("hexdump -C test.txt\n"); state = HEXDUMP_CHECK; pendingLine = "";} break;
|
||||
case HEXDUMP_CHECK: if (pendingLineContain("00000000 6d 69 61 6f 75 0a ")) { pushCin(""); state = PASS; pendingLine = "";} break;
|
||||
case PASS: if (pendingLineContain("# ")) { pass(); } break;
|
||||
}
|
||||
if(c == '\n' || pendingLine.length() > 200) pendingLine = "";
|
||||
}
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
string riscvTestMain[] = {
|
||||
|
|
@ -3490,7 +3553,7 @@ int main(int argc, char **argv, char **env) {
|
|||
soc.loadBin(DTB, 0xC3000000);
|
||||
soc.loadBin(RAMDISK, 0xC2000000);
|
||||
#endif
|
||||
//soc.setIStall(true); //TODO It currently improve speed but should be removed later
|
||||
//soc.setIStall(true);
|
||||
//soc.setDStall(true);
|
||||
soc.bootAt(0x80000000);
|
||||
soc.run(0);
|
||||
|
|
@ -3500,6 +3563,10 @@ int main(int argc, char **argv, char **env) {
|
|||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
// #ifdef MMU
|
||||
// redo(REDO,WorkspaceRegression("mmu").withRiscvRef()->loadHex("../raw/mmu/build/mmu.hex")->bootAt(0x80000000u)->run(50e3););
|
||||
// #endif
|
||||
|
|
@ -3722,15 +3789,36 @@ int main(int argc, char **argv, char **env) {
|
|||
queue <std::function<void()>> tasksSelected(std::deque<std::function<void()>>(tasks.begin(), tasks.end()));
|
||||
multiThreadedExecute(tasksSelected);
|
||||
#endif
|
||||
|
||||
#if defined(LINUX_REGRESSION)
|
||||
{
|
||||
|
||||
LinuxRegression soc("linux");
|
||||
#ifndef DEBUG_PLUGIN_EXTERNAL
|
||||
soc.withRiscvRef();
|
||||
soc.loadBin(EMULATOR, 0x80000000);
|
||||
soc.loadBin(VMLINUX, 0xC0000000);
|
||||
soc.loadBin(DTB, 0xC3000000);
|
||||
soc.loadBin(RAMDISK, 0xC2000000);
|
||||
#endif
|
||||
//soc.setIStall(true);
|
||||
//soc.setDStall(true);
|
||||
soc.bootAt(0x80000000);
|
||||
soc.run(153995602l*6);
|
||||
// soc.run((470000000l + 2000000) / 2);
|
||||
// soc.run(438700000l/2);
|
||||
}
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
uint64_t duration = timer_end(startedAt);
|
||||
cout << endl << "****************************************************************" << endl;
|
||||
cout << "Had simulate " << Workspace::cycles << " clock cycles in " << duration*1e-9 << " s (" << Workspace::cycles / (duration*1e-6) << " Khz)" << endl;
|
||||
if(Workspace::successCounter == Workspace::testsCounter)
|
||||
cout << "SUCCESS " << Workspace::successCounter << "/" << Workspace::testsCounter << endl;
|
||||
cout << "REGRESSION SUCCESS " << Workspace::successCounter << "/" << Workspace::testsCounter << endl;
|
||||
else
|
||||
cout<< "FAILURE " << Workspace::testsCounter - Workspace::successCounter << "/" << Workspace::testsCounter << endl;
|
||||
cout<< "REGRESSION FAILURE " << Workspace::testsCounter - Workspace::successCounter << "/" << Workspace::testsCounter << endl;
|
||||
cout << "****************************************************************" << endl << endl;
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -34,6 +34,7 @@ COMPRESSED?=no
|
|||
SUPERVISOR?=no
|
||||
STOP_ON_ERROR?=no
|
||||
COREMARK=no
|
||||
WITH_USER_IO?=no
|
||||
|
||||
ADDCFLAGS += -CFLAGS -DIBUS_${IBUS}
|
||||
ADDCFLAGS += -CFLAGS -DDBUS_${DBUS}
|
||||
|
|
@ -66,6 +67,31 @@ ifeq ($(LINUX_SOC),yes)
|
|||
ADDCFLAGS += -CFLAGS -DEMULATOR='\"$(EMULATOR)\"'
|
||||
endif
|
||||
|
||||
ARCH_LINUX=rv32i
|
||||
ifeq ($(MUL),yes)
|
||||
ifeq ($(DIV),yes)
|
||||
ARCH_LINUX:=$(ARCH_LINUX)m
|
||||
endif
|
||||
endif
|
||||
ARCH_LINUX:=$(ARCH_LINUX)a
|
||||
ifeq ($(COMPRESSED),yes)
|
||||
ARCH_LINUX:=$(ARCH_LINUX)c
|
||||
endif
|
||||
|
||||
ifeq ($(LINUX_REGRESSION),yes)
|
||||
ifneq ($(ARCH_LINUX),rv32iac)
|
||||
ifneq ($(ARCH_LINUX),rv32ia)
|
||||
ADDCFLAGS += -CFLAGS -DLINUX_REGRESSION
|
||||
ADDCFLAGS += -CFLAGS -DARCH_LINUX='\"$(ARCH_LINUX)\"'
|
||||
ADDCFLAGS += -CFLAGS -DVMLINUX='\"../../resources/VexRiscvRegressionData/sim/linux/$(ARCH_LINUX)/Image\"'
|
||||
ADDCFLAGS += -CFLAGS -DDTB='\"../../resources/VexRiscvRegressionData/sim/linux/$(ARCH_LINUX)/rv32.dtb\"'
|
||||
ADDCFLAGS += -CFLAGS -DRAMDISK='\"../../resources/VexRiscvRegressionData/sim/linux/$(ARCH_LINUX)/rootfs.cpio\"'
|
||||
ADDCFLAGS += -CFLAGS -DEMULATOR='\"../../resources/VexRiscvRegressionData/sim/linux/emulator/emulator.bin\"'
|
||||
endif
|
||||
endif
|
||||
endif
|
||||
|
||||
|
||||
ifeq ($(FLOW_INFO),yes)
|
||||
ADDCFLAGS += -CFLAGS -DFLOW_INFO
|
||||
endif
|
||||
|
|
@ -93,6 +119,10 @@ endif
|
|||
ifeq ($(IBUS_TC),yes)
|
||||
ADDCFLAGS += -CFLAGS -DIBUS_TC=yes
|
||||
endif
|
||||
ifeq ($(WITH_USER_IO),yes)
|
||||
ADDCFLAGS += -CFLAGS -DWITH_USER_IO=yes
|
||||
endif
|
||||
|
||||
|
||||
ifeq ($(COMPRESSED),yes)
|
||||
ADDCFLAGS += -CFLAGS -DCOMPRESSED
|
||||
|
|
|
|||
|
|
@ -0,0 +1 @@
|
|||
Subproject commit 77b66d304f888369176fb9ac2f9d6302dd4d276d
|
||||
|
|
@ -49,6 +49,11 @@ object VexRiscvUniverse{
|
|||
val universes = List(CATCH_ALL, MMU)
|
||||
}
|
||||
|
||||
|
||||
object Hack{
|
||||
var dCounter = 0
|
||||
}
|
||||
|
||||
class ShiftDimension extends VexRiscvDimension("Shift") {
|
||||
override def randomPositionImpl(universes: Seq[ConfigUniverse], r: Random) = random(r, List(
|
||||
new VexRiscvPosition("FullLate") {
|
||||
|
|
@ -287,13 +292,14 @@ class IBusDimension extends VexRiscvDimension("IBus") {
|
|||
override def instructionAnticipatedOk() = injectorStage
|
||||
}
|
||||
} else {
|
||||
val catchAll = universes.contains(VexRiscvUniverse.CATCH_ALL)
|
||||
val compressed = r.nextBoolean()
|
||||
val tighlyCoupled = r.nextBoolean()
|
||||
val tighlyCoupled = r.nextBoolean() && !catchAll
|
||||
// val tighlyCoupled = false
|
||||
val prediction = random(r, List(NONE, STATIC, DYNAMIC, DYNAMIC_TARGET))
|
||||
val catchAll = universes.contains(VexRiscvUniverse.CATCH_ALL)
|
||||
val relaxedPcCalculation, twoCycleCache, injectorStage = r.nextBoolean()
|
||||
val twoCycleRam = r.nextBoolean() && twoCycleCache
|
||||
val bytePerLine = List(8,16,32,64)(r.nextInt(4))
|
||||
var cacheSize = 0
|
||||
var wayCount = 0
|
||||
do{
|
||||
|
|
@ -301,7 +307,7 @@ class IBusDimension extends VexRiscvDimension("IBus") {
|
|||
wayCount = 1 << r.nextInt(3)
|
||||
}while(cacheSize/wayCount < 512 || (catchAll && cacheSize/wayCount > 4096))
|
||||
|
||||
new VexRiscvPosition("Cached" + (if(twoCycleCache) "2cc" else "") + (if(injectorStage) "Injstage" else "") + (if(twoCycleRam) "2cr" else "") + "S" + cacheSize + "W" + wayCount + (if(relaxedPcCalculation) "Relax" else "") + (if(compressed) "Rvc" else "") + prediction.getClass.getTypeName().replace("$","")+ (if(tighlyCoupled)"Tc" else "")) with InstructionAnticipatedPosition{
|
||||
new VexRiscvPosition("Cached" + (if(twoCycleCache) "2cc" else "") + (if(injectorStage) "Injstage" else "") + (if(twoCycleRam) "2cr" else "") + "S" + cacheSize + "W" + wayCount + "BPL" + bytePerLine + (if(relaxedPcCalculation) "Relax" else "") + (if(compressed) "Rvc" else "") + prediction.getClass.getTypeName().replace("$","")+ (if(tighlyCoupled)"Tc" else "")) with InstructionAnticipatedPosition{
|
||||
override def testParam = "IBUS=CACHED" + (if(compressed) " COMPRESSED=yes" else "") + (if(tighlyCoupled)" IBUS_TC=yes" else "")
|
||||
override def applyOn(config: VexRiscvConfig): Unit = {
|
||||
val p = new IBusCachedPlugin(
|
||||
|
|
@ -313,7 +319,7 @@ class IBusDimension extends VexRiscvDimension("IBus") {
|
|||
memoryTranslatorPortConfig = mmuConfig,
|
||||
config = InstructionCacheConfig(
|
||||
cacheSize = cacheSize,
|
||||
bytePerLine = 32,
|
||||
bytePerLine = bytePerLine,
|
||||
wayCount = wayCount,
|
||||
addressWidth = 32,
|
||||
cpuDataWidth = 32,
|
||||
|
|
@ -344,32 +350,37 @@ class DBusDimension extends VexRiscvDimension("DBus") {
|
|||
val mmuConfig = if(catchAll) MmuPortConfig( portTlbSize = 4) else null
|
||||
|
||||
if(r.nextDouble() < 0.4){
|
||||
val withLrSc = catchAll
|
||||
val earlyInjection = r.nextBoolean()
|
||||
new VexRiscvPosition("Simple" + (if(earlyInjection) "Early" else "Late")) {
|
||||
override def testParam = "DBUS=SIMPLE"
|
||||
override def testParam = "DBUS=SIMPLE " + (if(withLrSc) "LRSC=yes " else "")
|
||||
override def applyOn(config: VexRiscvConfig): Unit = config.plugins += new DBusSimplePlugin(
|
||||
catchAddressMisaligned = catchAll,
|
||||
catchAccessFault = catchAll,
|
||||
earlyInjection = earlyInjection,
|
||||
memoryTranslatorPortConfig = mmuConfig
|
||||
memoryTranslatorPortConfig = mmuConfig,
|
||||
withLrSc = withLrSc
|
||||
)
|
||||
// override def isCompatibleWith(positions: Seq[ConfigPosition[VexRiscvConfig]]) = catchAll == positions.exists(_.isInstanceOf[CatchAllPosition])
|
||||
}
|
||||
} else {
|
||||
val bytePerLine = List(8,16,32,64)(r.nextInt(4))
|
||||
var cacheSize = 0
|
||||
var wayCount = 0
|
||||
val withLrSc = catchAll
|
||||
val withAmo = catchAll && r.nextBoolean()
|
||||
do{
|
||||
cacheSize = 512 << r.nextInt(5)
|
||||
wayCount = 1 << r.nextInt(3)
|
||||
}while(cacheSize/wayCount < 512 || (catchAll && cacheSize/wayCount > 4096))
|
||||
new VexRiscvPosition("Cached" + "S" + cacheSize + "W" + wayCount) {
|
||||
override def testParam = "DBUS=CACHED"
|
||||
new VexRiscvPosition("Cached" + "S" + cacheSize + "W" + wayCount + "BPL" + bytePerLine) {
|
||||
override def testParam = "DBUS=CACHED " + (if(withLrSc) "LRSC=yes " else "") + (if(withAmo) "AMO=yes " else "")
|
||||
|
||||
override def applyOn(config: VexRiscvConfig): Unit = {
|
||||
config.plugins += new DBusCachedPlugin(
|
||||
config = new DataCacheConfig(
|
||||
cacheSize = cacheSize,
|
||||
bytePerLine = 32,
|
||||
bytePerLine = bytePerLine,
|
||||
wayCount = wayCount,
|
||||
addressWidth = 32,
|
||||
cpuDataWidth = 32,
|
||||
|
|
@ -377,7 +388,8 @@ class DBusDimension extends VexRiscvDimension("DBus") {
|
|||
catchAccessError = catchAll,
|
||||
catchIllegal = catchAll,
|
||||
catchUnaligned = catchAll,
|
||||
withLrSc = false
|
||||
withLrSc = withLrSc,
|
||||
withAmo = withAmo
|
||||
),
|
||||
memoryTranslatorPortConfig = mmuConfig
|
||||
)
|
||||
|
|
@ -421,14 +433,14 @@ class MmuDimension extends VexRiscvDimension("DBus") {
|
|||
|
||||
trait CatchAllPosition
|
||||
|
||||
//TODO CSR without exception
|
||||
|
||||
class CsrDimension(freertos : String) extends VexRiscvDimension("Csr") {
|
||||
override def randomPositionImpl(universes: Seq[ConfigUniverse], r: Random) = {
|
||||
val catchAll = universes.contains(VexRiscvUniverse.CATCH_ALL)
|
||||
if(catchAll){
|
||||
new VexRiscvPosition("All") with CatchAllPosition{
|
||||
override def applyOn(config: VexRiscvConfig): Unit = config.plugins += new CsrPlugin(CsrPluginConfig.linuxFull(0x80000020l))
|
||||
override def testParam = s"FREERTOS=$freertos"
|
||||
override def testParam = s"FREERTOS=$freertos LINUX_REGRESSION=yes SUPERVISOR=yes"
|
||||
}
|
||||
} else if(r.nextDouble() < 0.2){
|
||||
new VexRiscvPosition("AllNoException") with CatchAllPosition{
|
||||
|
|
@ -504,7 +516,7 @@ class TestIndividualFeatures extends FunSuite {
|
|||
new HazardDimension,
|
||||
new RegFileDimension,
|
||||
new SrcDimension,
|
||||
new CsrDimension(sys.env.getOrElse("VEXRISCV_REGRESSION_FREERTOS_COUNT", "yes")),
|
||||
new CsrDimension("no"),//sys.env.getOrElse("VEXRISCV_REGRESSION_FREERTOS_COUNT", "4")), TODO
|
||||
new DecoderDimension,
|
||||
new DebugDimension,
|
||||
new MmuDimension
|
||||
|
|
@ -541,14 +553,14 @@ class TestIndividualFeatures extends FunSuite {
|
|||
|
||||
|
||||
test(prefix + name + "_test") {
|
||||
val debug = false
|
||||
val stdCmd = (if(debug) "make clean run REDO=1 TRACE=yes TRACE_ACCESS=yes STOP_ON_ERROR=yes DHRYSTONE=no THREAD_COUNT=1 TRACE_START=0 " else s"make clean run REDO=10 TRACE=no THREAD_COUNT=${sys.env.getOrElse("VEXRISCV_REGRESSION_THREAD_COUNT", Runtime.getRuntime().availableProcessors().toString)} ") + s" SEED=${testSeed} "
|
||||
val debug = true
|
||||
val stdCmd = (s"make clean run WITH_USER_IO=no REDO=10 TRACE=${if(debug) "yes" else "no"} TRACE_START=9999924910246l FLOW_INFO=no STOP_ON_ERROR=no DHRYSTONE=yes COREMARK=yes THREAD_COUNT=${sys.env.getOrElse("VEXRISCV_REGRESSION_THREAD_COUNT", Runtime.getRuntime().availableProcessors().toString)} ") + s" SEED=${testSeed} "
|
||||
// val stdCmd = "make clean run REDO=40 DHRYSTONE=no STOP_ON_ERROR=yes TRACE=yess "
|
||||
|
||||
val testCmd = stdCmd + (positionsToApply).map(_.testParam).mkString(" ")
|
||||
println(testCmd)
|
||||
val str = doCmd(testCmd)
|
||||
assert(!str.contains("FAIL") && !str.contains("Broken pipe"))
|
||||
assert(str.contains("REGRESSION SUCCESS") && !str.contains("Broken pipe"))
|
||||
// val intFind = "(\\d+\\.?)+".r
|
||||
// val dmips = intFind.findFirstIn("DMIPS per Mhz\\: (\\d+.?)+".r.findAllIn(str).toList.last).get.toDouble
|
||||
}
|
||||
|
|
@ -556,8 +568,8 @@ class TestIndividualFeatures extends FunSuite {
|
|||
|
||||
// dimensions.foreach(d => d.positions.foreach(p => p.dimension = d))
|
||||
|
||||
// val testId : Option[mutable.HashSet[Int]] = None
|
||||
// val seed = Random.nextLong()
|
||||
val testId : Option[mutable.HashSet[Int]] = None
|
||||
val seed = Random.nextLong()
|
||||
|
||||
// val testId = Some(mutable.HashSet(18,34,77,85,118,129,132,134,152,167,175,188,191,198,199)) //37/29 sp_flop_rv32i_O3
|
||||
//val testId = Some(mutable.HashSet(18))
|
||||
|
|
@ -565,13 +577,6 @@ class TestIndividualFeatures extends FunSuite {
|
|||
// val seed = -2412372746600605141l
|
||||
|
||||
|
||||
//// val testId = Some(mutable.HashSet[Int](0,28,45,93))
|
||||
val testId = Some(mutable.HashSet[Int](69, 43))
|
||||
//val testId = Some(mutable.HashSet[Int]( 43))
|
||||
val seed = -8485282932516819277l
|
||||
|
||||
|
||||
|
||||
val rand = new Random(seed)
|
||||
|
||||
test("Info"){
|
||||
|
|
@ -589,6 +594,7 @@ class TestIndividualFeatures extends FunSuite {
|
|||
val testSeed = rand.nextInt()
|
||||
if(testId.isEmpty || testId.get.contains(i))
|
||||
doTest(positions," random_" + i + "_", testSeed)
|
||||
Hack.dCounter += 1
|
||||
}
|
||||
|
||||
// println(s"${usedPositions.size}/$positionsCount positions")
|
||||
|
|
|
|||
Loading…
Reference in New Issue