fpu integration wip, got mandelbrot to work in linux with no inline (crash when inlined)
This commit is contained in:
Dolu1990
parent
8537d18b16
commit
e504afbf18
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@ -33,7 +33,7 @@ import vexriscv.ip.fpu.FpuParameter
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object TestsWorkspace {
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def main(args: Array[String]) {
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SpinalConfig().generateVerilog {
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// make clean all REDO=10 CSR=no MMU=no COREMARK=no RVF=no REDO=1 DBUS_LOAD_DATA_WIDTH=64 DBUS_STORE_DATA_WIDTH=64 DEBUG=ye TRACE=ye
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// make clean all REDO=10 CSR=no MMU=no COREMARK=no RVF=yes RVD=yes REDO=1 DBUS_LOAD_DATA_WIDTH=64 DBUS_STORE_DATA_WIDTH=64 DEBUG=ye TRACE=ye
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val config = VexRiscvConfig(
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plugins = List(
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new IBusCachedPlugin(
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@ -15,12 +15,13 @@ import spinal.lib.generator.Handle
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import spinal.lib.misc.plic.PlicMapping
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import spinal.lib.system.debugger.SystemDebuggerConfig
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import vexriscv.ip.{DataCacheAck, DataCacheConfig, DataCacheMemBus, InstructionCache, InstructionCacheConfig}
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import vexriscv.plugin.{BranchPlugin, CsrAccess, CsrPlugin, CsrPluginConfig, DBusCachedPlugin, DBusSimplePlugin, DYNAMIC_TARGET, DebugPlugin, DecoderSimplePlugin, FullBarrelShifterPlugin, HazardSimplePlugin, IBusCachedPlugin, IBusSimplePlugin, IntAluPlugin, MmuPlugin, MmuPortConfig, MulDivIterativePlugin, MulPlugin, RegFilePlugin, STATIC, SrcPlugin, StaticMemoryTranslatorPlugin, YamlPlugin}
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import vexriscv.plugin.{BranchPlugin, CsrAccess, CsrPlugin, CsrPluginConfig, DBusCachedPlugin, DBusSimplePlugin, DYNAMIC_TARGET, DebugPlugin, DecoderSimplePlugin, FpuPlugin, FullBarrelShifterPlugin, HazardSimplePlugin, IBusCachedPlugin, IBusSimplePlugin, IntAluPlugin, MmuPlugin, MmuPortConfig, MulDivIterativePlugin, MulPlugin, RegFilePlugin, STATIC, SrcPlugin, StaticMemoryTranslatorPlugin, YamlPlugin}
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import vexriscv.{Riscv, VexRiscv, VexRiscvBmbGenerator, VexRiscvConfig, plugin}
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import scala.collection.mutable
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import scala.collection.mutable.ArrayBuffer
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import spinal.lib.generator._
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import vexriscv.ip.fpu.FpuParameter
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case class VexRiscvSmpClusterParameter(cpuConfigs : Seq[VexRiscvConfig], withExclusiveAndInvalidation : Boolean, forcePeripheralWidth : Boolean = true, outOfOrderDecoder : Boolean = true)
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@ -163,10 +164,15 @@ object VexRiscvSmpClusterGen {
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earlyBranch : Boolean = false,
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dBusCmdMasterPipe : Boolean = false,
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withMmu : Boolean = true,
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withSupervisor : Boolean = true
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withSupervisor : Boolean = true,
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withFloat : Boolean = false,
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withDouble : Boolean = false,
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externalFpu : Boolean = true
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) = {
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assert(iCacheSize/iCacheWays <= 4096, "Instruction cache ways can't be bigger than 4096 bytes")
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assert(dCacheSize/dCacheWays <= 4096, "Data cache ways can't be bigger than 4096 bytes")
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assert(!(withDouble && !withFloat))
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val config = VexRiscvConfig(
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plugins = List(
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if(withMmu)new MmuPlugin(
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@ -262,7 +268,7 @@ object VexRiscvSmpClusterGen {
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mulUnrollFactor = 32,
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divUnrollFactor = 1
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),
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new CsrPlugin(CsrPluginConfig.openSbi(mhartid = hartId, misa = Riscv.misaToInt("imas")).copy(utimeAccess = CsrAccess.READ_ONLY)),
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new CsrPlugin(CsrPluginConfig.openSbi(mhartid = hartId, misa = Riscv.misaToInt(s"ima${if(withFloat) "f" else ""}${if(withDouble) "d" else ""}s")).copy(utimeAccess = CsrAccess.READ_ONLY)),
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new BranchPlugin(
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earlyBranch = earlyBranch,
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catchAddressMisaligned = true,
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@ -271,6 +277,11 @@ object VexRiscvSmpClusterGen {
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new YamlPlugin(s"cpu$hartId.yaml")
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)
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)
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if(withFloat) config.plugins += new FpuPlugin(
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externalFpu = true,
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p = FpuParameter(withDouble = withDouble)
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)
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config
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}
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@ -675,7 +675,7 @@ class DataCache(val p : DataCacheConfig, mmuParameter : MemoryTranslatorBusParam
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val rspSync = True
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val rspLast = True
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val memCmdSent = RegInit(False) setWhen (io.mem.cmd.ready) clearWhen (!io.cpu.writeBack.isStuck)
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val memCmdSent = RegInit(False) setWhen (io.mem.cmd.fire) clearWhen (!io.cpu.writeBack.isStuck)
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val pending = withExclusive generate new Area{
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val counter = Reg(UInt(log2Up(pendingMax) + 1 bits)) init(0)
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val counterNext = counter + U(io.mem.cmd.fire && io.mem.cmd.last) - ((io.mem.rsp.valid && io.mem.rsp.last) ? (io.mem.rsp.aggregated +^ 1) | 0)
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@ -207,7 +207,7 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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arbiterOutput.source := arbiter.io.chosen
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arbiterOutput.payload.assignSomeByName(arbiter.io.output.payload)
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val s0 = arbiterOutput.pipelined(m2s = true, s2m = true)
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val s0 = arbiterOutput.pipelined(m2s = true, s2m = true) //TODO may need to remove m2s for store latency
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val useRs1, useRs2, useRs3, useRd = False
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switch(s0.opcode){
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is(p.Opcode.LOAD) { useRd := True }
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@ -287,28 +287,28 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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}
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val decode = new Area{
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val input = read.output.combStage()
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val input = read.output/*.s2mPipe()*/.combStage()
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input.ready := False
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val loadHit = List(FpuOpcode.LOAD, FpuOpcode.FMV_W_X, FpuOpcode.I2F).map(input.opcode === _).orR
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val load = Stream(LoadInput())
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load.valid := input.valid && loadHit
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input.ready setWhen(loadHit && load.ready)
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load.payload.assignSomeByName(read.output.payload)
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load.payload.assignSomeByName(input.payload)
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load.i2f := input.opcode === FpuOpcode.I2F
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val shortPipHit = List(FpuOpcode.STORE, FpuOpcode.F2I, FpuOpcode.CMP, FpuOpcode.MIN_MAX, FpuOpcode.SGNJ, FpuOpcode.FMV_X_W, FpuOpcode.FCLASS, FpuOpcode.FCVT_X_X).map(input.opcode === _).orR
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val shortPip = Stream(ShortPipInput())
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input.ready setWhen(shortPipHit && shortPip.ready)
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shortPip.valid := input.valid && shortPipHit
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shortPip.payload.assignSomeByName(read.output.payload)
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shortPip.payload.assignSomeByName(input.payload)
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val divSqrtHit = input.opcode === p.Opcode.DIV || input.opcode === p.Opcode.SQRT
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val divSqrt = Stream(DivSqrtInput())
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if(p.withDivSqrt) {
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input.ready setWhen (divSqrtHit && divSqrt.ready)
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divSqrt.valid := input.valid && divSqrtHit
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divSqrt.payload.assignSomeByName(read.output.payload)
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divSqrt.payload.assignSomeByName(input.payload)
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divSqrt.div := input.opcode === p.Opcode.DIV
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}
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@ -324,15 +324,15 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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divSqrtToMul.ready := mul.ready
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mul.payload := divSqrtToMul.payload
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when(!divSqrtToMul.valid) {
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mul.payload.assignSomeByName(read.output.payload)
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mul.payload.assignSomeByName(input.payload)
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mul.add := fmaHit
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mul.divSqrt := False
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mul.msb1 := True
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mul.msb2 := True
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mul.rs2.sign.allowOverride();
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mul.rs2.sign := read.output.rs2.sign ^ input.arg(0)
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mul.rs2.sign := input.rs2.sign ^ input.arg(0)
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mul.rs3.sign.allowOverride();
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mul.rs3.sign := read.output.rs3.sign ^ input.arg(1)
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mul.rs3.sign := input.rs3.sign ^ input.arg(1)
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}
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}
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@ -348,9 +348,9 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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mulToAdd.ready := add.ready
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add.payload := mulToAdd.payload
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when(!mulToAdd.valid) {
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add.payload.assignSomeByName(read.output.payload)
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add.payload.assignSomeByName(input.payload)
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add.rs2.sign.allowOverride;
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add.rs2.sign := read.output.rs2.sign ^ input.arg(0)
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add.rs2.sign := input.rs2.sign ^ input.arg(0)
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}
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}
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}
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@ -578,7 +578,7 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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val input = UInt(p.internalMantissaSize+1 max 33 bits).assignDontCare()
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var logic = input
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val scrap = Reg(Bool)
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for(i <- by.range){
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for(i <- by.range.reverse){
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scrap setWhen(by(i) && logic(0, 1 << i bits) =/= 0)
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logic \= by(i) ? (logic |>> (BigInt(1) << i)) | logic
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}
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@ -809,11 +809,13 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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List(FpuOpcode.CMP, FpuOpcode.MIN_MAX).map(input.opcode === _).orR && rs2NanNv
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flag.NV setWhen(input.valid && nv)
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input.ready := !halt && (toFpuRf ? rfOutput.ready | io.port.map(_.rsp.ready).read(input.source))
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val rspStreams = Vec(Stream(FpuRsp(p)), portCount)
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input.ready := !halt && (toFpuRf ? rfOutput.ready | rspStreams.map(_.ready).read(input.source))
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for(i <- 0 until portCount){
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def rsp = io.port(i).rsp
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def rsp = rspStreams(i)
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rsp.valid := input.valid && input.source === i && !toFpuRf && !halt
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rsp.value := result
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io.port(i).rsp << rsp.stage()
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completion(i).increments += (RegNext(rsp.fire) init(False))
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}
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}
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@ -940,7 +942,7 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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}
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val divSqrt = p.withDivSqrt generate new Area {
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val input = decode.divSqrt.stage()
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val input = decode.divSqrt.halfPipe()
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val aproxWidth = 8
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val aproxDepth = 64
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@ -1142,7 +1144,7 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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val rs1ExponentEqual = input.rs1.exponent === input.rs2.exponent
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val rs1MantissaBigger = input.rs1.mantissa > input.rs2.mantissa
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val absRs1Bigger = ((rs1ExponentBigger || rs1ExponentEqual && rs1MantissaBigger) && !input.rs1.isZero || input.rs1.isInfinity) && !input.rs2.isInfinity
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val shiftBy = rs1ExponentBigger ? (0-exp21) | exp21
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val shiftBy = exp21.asSInt.abs//rs1ExponentBigger ? (0-exp21) | exp21
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val shiftOverflow = (shiftBy >= p.internalMantissaSize+3)
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val passThrough = shiftOverflow || (input.rs1.isZero) || (input.rs2.isZero)
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@ -1153,8 +1155,8 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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val xMantissa = U"1" @@ (rs1ExponentBigger ? input.rs1.mantissa | input.rs2.mantissa) @@ U"00"
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val yMantissaUnshifted = U"1" @@ (rs1ExponentBigger ? input.rs2.mantissa | input.rs1.mantissa) @@ U"00"
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var yMantissa = CombInit(yMantissaUnshifted)
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val roundingScrap = CombInit(shiftOverflow)
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for(i <- 0 until log2Up(p.internalMantissaSize)){
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val roundingScrap = False
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for(i <- log2Up(p.internalMantissaSize) - 1 downto 0){
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roundingScrap setWhen(shiftBy(i) && yMantissa(0, 1 << i bits) =/= 0)
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yMantissa \= shiftBy(i) ? (yMantissa |>> (BigInt(1) << i)) | yMantissa
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}
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@ -1181,6 +1183,25 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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val xSigned = xMantissa.twoComplement(xSign) //TODO Is that necessary ?
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val ySigned = ((ySign ## Mux(ySign, ~yMantissa, yMantissa)).asUInt + (ySign && !roundingScrap).asUInt).asSInt //rounding here
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output.xyMantissa := U(xSigned +^ ySigned).trim(1 bits)
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}
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class OhOutput extends MathOutput{
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// val shiftOh = Vec(Bool, p.internalMantissaSize+4)
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val shift = UInt(log2Up(p.internalMantissaSize+4) bits)
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}
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val oh = new Area {
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val input = math.output.stage()
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val output = input.swapPayload(new OhOutput)
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output.payload.assignSomeByName(input.payload)
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import input.payload._
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val shiftOh = OHMasking.first(output.xyMantissa.asBools.reverse) //The OhMasking.first can be processed in parallel to the xyMantissa carry chaine
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// output.shiftOh := shiftOh
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val shift = OHToUInt(shiftOh)
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output.shift := shift
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}
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@ -1193,13 +1214,11 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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}
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val norm = new Area{
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val input = math.output.stage()
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val input = oh.output.stage()
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val output = input.swapPayload(new NormOutput)
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output.payload.assignSomeByName(input.payload)
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import input.payload._
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val shiftOh = OHMasking.first(xyMantissa.asBools.reverse)
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val shift = OHToUInt(shiftOh)
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output.mantissa := (xyMantissa |<< shift)
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output.exponent := xyExponent -^ shift + 1
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output.forceInfinity := (input.rs1.isInfinity || input.rs2.isInfinity)
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@ -1210,7 +1229,7 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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}
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val result = new Area {
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val input = norm.output.stage()
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val input = norm.output.pipelined()
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val output = input.swapPayload(new MergeInput())
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import input.payload._
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@ -1251,7 +1270,7 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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inputs += load.s1.output.stage()
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if(p.withAdd) (inputs += add.result.output)
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if(p.withMul) (inputs += mul.result.output)
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if(p.withShortPipMisc) (inputs += shortPip.rfOutput)
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if(p.withShortPipMisc) (inputs += shortPip.rfOutput.pipelined(m2s = true))
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val arbitrated = StreamArbiterFactory.lowerFirst.noLock.on(inputs)
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val isCommited = rf.lock.map(_.commited).read(arbitrated.lockId)
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val commited = arbitrated.haltWhen(!isCommited).toFlow
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@ -1301,7 +1320,7 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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val mantissaRange = p.internalMantissaSize downto 1
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val adderMantissa = input.value.mantissa(mantissaRange) & (mantissaIncrement ? ~(exactMask.trim(1) >> 1) | input.value.mantissa(mantissaRange).maxValue)
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val adderRightOp = (mantissaIncrement ? (exactMask >> 1)| U(0)).resize(p.internalMantissaSize bits)
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val adder = (input.value.exponent @@ adderMantissa) + adderRightOp + U(mantissaIncrement)
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val adder = KeepAttribute(KeepAttribute(input.value.exponent @@ adderMantissa) + KeepAttribute(adderRightOp) + KeepAttribute(U(mantissaIncrement)))
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math.special := input.value.special
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math.sign := input.value.sign
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math.exponent := adder(p.internalMantissaSize, p.internalExponentSize bits)
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@ -138,6 +138,12 @@ case class FpuFlags() extends Bundle{
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case class FpuCompletion() extends Bundle{
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val flag = FpuFlags()
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val count = UInt(2 bits)
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def stage() = {
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val ret = FpuCompletion().setCompositeName(this, "stage", true)
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ret := this
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ret
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}
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}
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case class FpuCmd(p : FpuParameter) extends Bundle{
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@ -72,6 +72,9 @@ class DBusCachedPlugin(val config : DataCacheConfig,
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MEMORY_WR -> False
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) ++ (if(catchSomething) List(HAS_SIDE_EFFECT -> True) else Nil)
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)
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if(withLrSc) decoderService.add(key, Seq(MEMORY_LRSC -> False))
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if(withAmo) decoderService.add(key, Seq(MEMORY_AMO -> False))
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}
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override def addStoreWordEncoding(key : MaskedLiteral): Unit = {
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val decoderService = pipeline.service(classOf[DecoderService])
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@ -91,6 +94,9 @@ class DBusCachedPlugin(val config : DataCacheConfig,
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MEMORY_WR -> True
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) ++ (if(catchSomething) List(HAS_SIDE_EFFECT -> True) else Nil)
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)
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if(withLrSc) decoderService.add(key, Seq(MEMORY_LRSC -> False))
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if(withAmo) decoderService.add(key, Seq(MEMORY_AMO -> False))
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}
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val bypassStoreList = ArrayBuffer[(Bool, Bits)]()
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@ -501,6 +507,7 @@ class DBusCachedPlugin(val config : DataCacheConfig,
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dBusAccess.rsp.error := cache.io.cpu.writeBack.unalignedAccess || cache.io.cpu.writeBack.accessError
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dBusAccess.rsp.redo := cache.io.cpu.redo
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component.addPrePopTask{() =>
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managementStage.input(IS_DBUS_SHARING).getDrivingReg clearWhen(dBusAccess.rsp.fire)
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when(forceDatapath){
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execute.output(REGFILE_WRITE_DATA) := dBusAccess.cmd.address.asBits
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}
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@ -157,13 +157,13 @@ class FpuPlugin(externalFpu : Boolean = false,
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import pipeline.config._
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import Riscv._
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val internal = !externalFpu generate pipeline plug new Area{
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val internal = (!externalFpu).generate (pipeline plug new Area{
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val fpu = FpuCore(1, p)
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fpu.io.port(0).cmd << port.cmd
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fpu.io.port(0).commit << port.commit
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fpu.io.port(0).rsp >> port.rsp
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fpu.io.port(0).completion <> port.completion
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}
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})
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val csr = pipeline plug new Area{
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@ -195,6 +195,7 @@ class FpuPlugin(externalFpu : Boolean = false,
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fs := 3 //DIRTY
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}
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service.rw(CSR.SSTATUS, 13, fs)
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service.rw(CSR.MSTATUS, 13, fs)
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}
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decode plug new Area{
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@ -259,7 +260,7 @@ class FpuPlugin(externalFpu : Boolean = false,
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|||
commit.write := arbitration.isValid && !arbitration.removeIt
|
||||
commit.sync := input(FPU_COMMIT_SYNC)
|
||||
|
||||
when(arbitration.isValid && !commit.ready){
|
||||
when(isCommit && !commit.ready){
|
||||
arbitration.haltByOther := True
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue