Rework CsrPlugin exception delegation
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@ -314,13 +314,15 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception
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val csrMapping = new CsrMapping()
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//Interruption specification data model
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//Interruption and exception data model
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case class Delegator(var enable : Bool, privilege : Int)
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case class InterruptSource(var cond : Bool, id : Int, privilege : Int, delegators : List[Delegator])
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var interruptSpecs = ArrayBuffer[InterruptSource]()
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case class InterruptSpec(var cond : Bool, id : Int, privilege : Int, delegators : List[Delegator])
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case class ExceptionSpec(id : Int, delegators : List[Delegator])
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var interruptSpecs = ArrayBuffer[InterruptSpec]()
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var exceptionSpecs = ArrayBuffer[ExceptionSpec]()
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def addInterrupt(cond : Bool, id : Int, privilege : Int, delegators : List[Delegator]): Unit = {
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interruptSpecs += InterruptSource(cond, id, privilege, delegators)
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interruptSpecs += InterruptSpec(cond, id, privilege, delegators)
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}
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override def r(csrAddress: Int, bitOffset: Int, that: Data): Unit = csrMapping.r(csrAddress, bitOffset, that)
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@ -464,8 +466,10 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception
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val minstret = Reg(UInt(64 bits)) randBoot()
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val medeleg = Reg(Bits(32 bits)) init(0)
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val medeleg = supervisorGen generate new Area {
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val IAM, IAF, II, LAM, LAF, SAM, SAF, EU, ES, IPF, LPF, SPF = RegInit(False)
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val mapping = mutable.HashMap(0 -> IAM, 1 -> IAF, 2 -> II, 4 -> LAM, 5 -> LAF, 6 -> SAM, 7 -> SAF, 8 -> EU, 9 -> ES, 12 -> IPF, 13 -> LPF, 15 -> SPF)
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}
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val mideleg = supervisorGen generate new Area {
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val ST, SE, SS = RegInit(False)
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}
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@ -493,7 +497,7 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception
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minstretAccess(CSR.MINSTRETH, minstret(63 downto 32))
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if(supervisorGen) {
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medelegAccess(CSR.MEDELEG, medeleg)
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for((id, enable) <- medeleg.mapping) medelegAccess(CSR.MEDELEG, id -> enable)
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midelegAccess(CSR.MIDELEG, 9 -> mideleg.SE, 5 -> mideleg.ST, 1 -> mideleg.SS)
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}
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@ -578,47 +582,14 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception
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addInterrupt(sip.STIP && sie.STIE, id = 5, privilege = 1, delegators = List(Delegator(mideleg.ST, 3)))
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addInterrupt(sip.SSIP && sie.SSIE, id = 1, privilege = 1, delegators = List(Delegator(mideleg.SS, 3)))
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addInterrupt(sip.SEIP_OR && sie.SEIE, id = 9, privilege = 1, delegators = List(Delegator(mideleg.SE, 3)))
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for((id, enable) <- medeleg.mapping) exceptionSpecs += ExceptionSpec(id, List(Delegator(enable, 3)))
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}
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addInterrupt(mip.MTIP && mie.MTIE, id = 7, privilege = 3, delegators = Nil)
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addInterrupt(mip.MSIP && mie.MSIE, id = 3, privilege = 3, delegators = Nil)
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addInterrupt(mip.MEIP && mie.MEIE, id = 11, privilege = 3, delegators = Nil)
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case class DelegatorModel(value : Bits, source : Int, target : Int)
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// def solveDelegators(delegators : Seq[DelegatorModel], id : Int, lowerBound : Int): UInt = {
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// val filtredDelegators = delegators.filter(_.target >= lowerBound)
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// val ret = U(lowerBound, 2 bits)
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// for(d <- filtredDelegators){
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// when(!d.value(id)){
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// ret := d.source
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// }
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// }
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// ret
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// }
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def solveDelegators(delegators : Seq[DelegatorModel], id : UInt, lowerBound : UInt): UInt = {
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if(delegators.isEmpty) return U"11"
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val ret = U(delegators.last.target, 2 bits)
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for(d <- delegators){
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when(!d.value(id) || d.target < lowerBound){
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ret := d.source
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}
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}
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ret
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// val ret = U"11"
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// var continue = True
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// for(d <- delegators){
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// continue = continue && d.value(id)
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// when(continue){
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// ret := d.source
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// }
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// }
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// ret.max(lowerBound)
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}
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val exceptionDelegators = ArrayBuffer[DelegatorModel]()
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if(medelegAccess.canWrite) exceptionDelegators += DelegatorModel(medeleg,3, 1)
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val mepcCaptureStage = if(exceptionPortsInfos.nonEmpty) lastStage else decode
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@ -629,7 +600,27 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception
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val exceptionValids = Vec(stages.map(s => Bool().setPartialName(s.getName())))
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val exceptionValidsRegs = Vec(stages.map(s => Reg(Bool).init(False).setPartialName(s.getName()))).allowUnsetRegToAvoidLatch
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val exceptionContext = Reg(ExceptionCause())
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val exceptionTargetPrivilege = solveDelegators(exceptionDelegators, exceptionContext.code, privilege)
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val exceptionTargetPrivilegeUncapped = U"11"
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switch(exceptionContext.code){
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for(s <- exceptionSpecs){
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is(s.id){
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var exceptionPrivilegs = if (supervisorGen) List(1, 3) else List(3)
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while(exceptionPrivilegs.length != 1){
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val p = exceptionPrivilegs.head
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if (exceptionPrivilegs.tail.forall(e => s.delegators.exists(_.privilege == e))) {
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val delegUpOn = s.delegators.filter(_.privilege > p).map(_.enable).fold(True)(_ && _)
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val delegDownOff = !s.delegators.filter(_.privilege <= p).map(_.enable).orR
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when(delegUpOn && delegDownOff) {
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exceptionTargetPrivilegeUncapped := p
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}
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}
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exceptionPrivilegs = exceptionPrivilegs.tail
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}
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}
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}
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}
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val exceptionTargetPrivilege = exceptionTargetPrivilegeUncapped.max(privilege)
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val groupedByStage = exceptionPortsInfos.map(_.stage).distinct.map(s => {
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val stagePortsInfos = exceptionPortsInfos.filter(_.stage == s).sortWith(_.priority > _.priority)
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