Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Add comments to the AesPlugin

This commit is contained in:
Dolu1990 2020-12-11 13:51:10 +01:00
parent 6da09967f8
commit eaff52b264
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/vexriscv/plugin/AesPlugin.scala
View File

@ -56,7 +56,7 @@ import vexriscv.{DecoderService, Stageable, VexRiscv}
* from a SoC running linux at 100 Mhz
* type 16 bytes 64 bytes 256 bytes 1024 bytes 8192 bytes 16384 bytes
* aes-256-cbc SW 492.58k 700.22k 796.41k 831.49k 830.09k 832.81k
* aes-256-cbc HW 1099.77k 2320.65k 3164.16k 3484.67k 3528.02k 3511.64k
* aes-256 cbc HW 1781.52k 2834.07k 3323.07k 3486.72k 3465.22k 3440.10k
*/
case class AesPlugin(encoding : MaskedLiteral = M"-----------------000-----0001011") extends Plugin[VexRiscv]{