Default linux config is now without RVC
Remove all linux usless CSR from the config Remove verilator instruction fetch check
This commit is contained in:
Charles Papon
parent
caa37a8028
commit
ece1e73547
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@ -40,13 +40,13 @@ cd VexRiscv
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Run regressions =>
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sbt "runMain vexriscv.demo.LinuxGen -r"
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cd src/test/cpp/regression
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make run IBUS=CACHED DBUS=CACHED DEBUG_PLUGIN=STD DHRYSTONE=yes SUPERVISOR=yes CSR=yes COMPRESSED=yes LRSC=yes AMO=yes REDO=10 TRACE=no
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make run IBUS=CACHED DBUS=CACHED DEBUG_PLUGIN=STD DHRYSTONE=yes SUPERVISOR=yes CSR=yes COMPRESSED=no LRSC=yes AMO=yes REDO=10 TRACE=no
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Run linux in simulation (Require the machime mode emulator compiled in SIM mode) =>
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sbt "runMain vexriscv.demo.LinuxGen"
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cd src/test/cpp/regression
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export BUILDROOT=/home/miaou/pro/riscv/buildrootSpinal
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make run IBUS=CACHED DBUS=CACHED DEBUG_PLUGIN=STD SUPERVISOR=yes CSR=yes COMPRESSED=yes LRSC=yes AMO=yes REDO=0 DHRYSTONE=no LINUX_SOC=yes EMULATOR=../../../main/c/emulator/build/emulator.bin VMLINUX=$BUILDROOT/output/images/Image DTB=$BUILDROOT/board/spinal/vexriscv_sim/rv32.dtb RAMDISK=$BUILDROOT/output/images/rootfs.cpio TRACE=no FLOW_INFO=no
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make run IBUS=CACHED DBUS=CACHED DEBUG_PLUGIN=STD SUPERVISOR=yes CSR=yes COMPRESSED=no LRSC=yes AMO=yes REDO=0 DHRYSTONE=no LINUX_SOC=yes EMULATOR=../../../main/c/emulator/build/emulator.bin VMLINUX=$BUILDROOT/output/images/Image DTB=$BUILDROOT/board/spinal/vexriscv_sim/rv32.dtb RAMDISK=$BUILDROOT/output/images/rootfs.cpio TRACE=no FLOW_INFO=no
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Run linux with QEMU (Require the machime mode emulator compiled in QEMU mode)
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export BUILDROOT=/home/miaou/pro/riscv/buildrootSpinal
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@ -114,6 +114,12 @@ RAMDISK=/home/miaou/pro/riscv/buildrootSpinal/output/images/rootfs.cpio TRACE=no
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make run IBUS=CACHED DBUS=CACHED DEBUG_PLUGIN=STD SUPERVISOR=yes CSR=yes COMPRESSED=yes LRSC=yes AMO=yes REDO=0 DHRYSTONE=no LINUX_SOC=yes DEBUG_PLUGIN_EXTERNAL=yes
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rm -rf cpio
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mkdir cpio
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cd cpio
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ls | cpio -ov > ../rootfs.cpio
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cpio -idv < ../rootfs.cpio
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*/
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@ -140,9 +146,9 @@ object LinuxGen {
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//Uncomment the whole IBusCachedPlugin and comment IBusSimplePlugin if you want cached iBus config
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new IBusCachedPlugin(
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resetVector = 0x80000000l,
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compressedGen = true,
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compressedGen = false,
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prediction = NONE,
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injectorStage = true,
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injectorStage = false,
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config = InstructionCacheConfig(
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cacheSize = 4096*1,
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bytePerLine = 32,
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@ -232,7 +238,7 @@ object LinuxGen {
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divUnrollFactor = 1
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),
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// new DivPlugin,
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new CsrPlugin(CsrPluginConfig.linux(0x80000020l).copy(ebreakGen = false)),
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new CsrPlugin(CsrPluginConfig.linuxMinimal(0x80000020l).copy(ebreakGen = false)),
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// new CsrPlugin(//CsrPluginConfig.all2(0x80000020l).copy(ebreakGen = true)/*
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// CsrPluginConfig(
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// catchIllegalAccess = false,
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@ -398,7 +404,7 @@ object LinuxSyntesisBench extends App{
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SpinalConfig(inlineRom=true).generateVerilog(new VexRiscv(LinuxGen.configFull(litex = false, withMmu = true)).setDefinitionName(getRtlPath().split("\\.").head))
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}
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val rtls = List(withoutMmu, withMmu)
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val rtls = List(/*withoutMmu, */withMmu)
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// val rtls = List(smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache)
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// val rtls = List(smallAndProductive, smallAndProductiveWithICache, fullNoMmuMaxPerf, fullNoMmu, full)
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// val rtls = List(fullNoMmu)
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@ -408,7 +414,7 @@ object LinuxSyntesisBench extends App{
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) ++ AlteraStdTargets(
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quartusCycloneIVPath = "/media/miaou/HD/linux/intelFPGA_lite/18.1/quartus/bin",
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quartusCycloneVPath = "/media/miaou/HD/linux/intelFPGA_lite/18.1/quartus/bin"
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) ++ IcestormStdTargets().take(1)
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) //++ IcestormStdTargets().take(1)
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Bench(rtls, targets, "/media/miaou/HD/linux/tmp")
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}
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@ -78,7 +78,46 @@ object CsrPluginConfig{
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def all : CsrPluginConfig = all(0x00000020l)
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def small : CsrPluginConfig = small(0x00000020l)
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def smallest : CsrPluginConfig = smallest(0x00000020l)
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def linux(mtVecInit : BigInt) = CsrPluginConfig(
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def linuxMinimal(mtVecInit : BigInt) = CsrPluginConfig(
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catchIllegalAccess = true,
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mvendorid = 1,
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marchid = 2,
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mimpid = 3,
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mhartid = 0,
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misaExtensionsInit = 0, //TODO
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misaAccess = CsrAccess.NONE, //Read required by some regressions
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mtvecAccess = CsrAccess.WRITE_ONLY, //Read required by some regressions
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mtvecInit = mtVecInit,
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mepcAccess = CsrAccess.READ_WRITE,
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mscratchGen = true,
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mcauseAccess = CsrAccess.READ_ONLY,
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mbadaddrAccess = CsrAccess.READ_ONLY,
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mcycleAccess = CsrAccess.NONE,
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minstretAccess = CsrAccess.NONE,
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ucycleAccess = CsrAccess.NONE,
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wfiGenAsWait = true,
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ecallGen = false,
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xtvecModeGen = false,
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noCsrAlu = false,
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wfiGenAsNop = false,
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ebreakGen = true,
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supervisorGen = true,
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sscratchGen = true,
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stvecAccess = CsrAccess.READ_WRITE,
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sepcAccess = CsrAccess.READ_WRITE,
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scauseAccess = CsrAccess.READ_WRITE,
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sbadaddrAccess = CsrAccess.READ_WRITE,
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scycleAccess = CsrAccess.NONE,
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sinstretAccess = CsrAccess.NONE,
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satpAccess = CsrAccess.NONE, //Implemented into the MMU plugin
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medelegAccess = CsrAccess.WRITE_ONLY,
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midelegAccess = CsrAccess.WRITE_ONLY,
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pipelineCsrRead = false,
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deterministicInteruptionEntry = false
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)
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def linuxFull(mtVecInit : BigInt) = CsrPluginConfig(
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catchIllegalAccess = true,
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mvendorid = 1,
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marchid = 2,
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@ -1093,7 +1093,6 @@ public:
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uint32_t seed;
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bool withInstructionReadCheck = true;
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Workspace* setIStall(bool enable) { iStall = enable; return this; }
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Workspace* setDStall(bool enable) { dStall = enable; return this; }
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@ -1402,9 +1401,9 @@ public:
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virtual void pass(){ throw success();}
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virtual void fail(){ throw std::exception();}
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virtual void fillSimELements();
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Workspace* noInstructionReadCheck(){withInstructionReadCheck = false; return this;}
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void dump(int i){
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#ifdef TRACE
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if(i == TRACE_START) cout << "START TRACE" << endl;
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if(i >= TRACE_START) tfp->dump(i);
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#endif
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}
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@ -1513,7 +1512,7 @@ public:
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currentTime = i;
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#ifdef FLOW_INFO
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if(i % 100000 == 0) cout << "PROGRESS TRACE_START=" << i << endl;
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if(i % 2000000 == 0) cout << "PROGRESS TRACE_START=" << i << endl;
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#endif
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@ -1604,17 +1603,6 @@ public:
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dump(i + 1);
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#ifndef COMPRESSED
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if(withInstructionReadCheck){
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if(top->VexRiscv->decode_arbitration_isValid && !top->VexRiscv->decode_arbitration_haltItself && !top->VexRiscv->decode_arbitration_flushAll){
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uint32_t expectedData;
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bool dummy;
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iBusAccess(top->VexRiscv->decode_PC, &expectedData, &dummy);
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assertEq(top->VexRiscv->decode_INSTRUCTION,expectedData);
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}
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}
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#endif
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checks();
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//top->eval();
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top->clk = 1;
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@ -2808,7 +2796,6 @@ public:
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loadHex("../../resources/hex/" + name + ".elf.hex");
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out32.open (name + ".out32");
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this->name = name;
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if(name == "I-FENCE.I-01") withInstructionReadCheck = false;
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}
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@ -3018,7 +3005,6 @@ public:
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DebugPluginTest() : WorkspaceRegression("DebugPluginTest") {
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loadHex("../../resources/hex/debugPlugin.hex");
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pthread_create(&clientThreadId, NULL, &clientThreadWrapper, this);
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noInstructionReadCheck();
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}
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virtual ~DebugPluginTest(){
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@ -3526,7 +3512,6 @@ int main(int argc, char **argv, char **env) {
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w.loadHex(RUN_HEX);
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w.withRiscvRef();
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#endif
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w.noInstructionReadCheck();
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//w.setIStall(false);
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//w.setDStall(false);
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@ -3604,11 +3589,11 @@ int main(int argc, char **argv, char **env) {
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#ifndef COMPRESSED
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uint32_t machineCsrRef[] = {1,11, 2,0x80000003u, 3,0x80000007u, 4,0x8000000bu, 5,6,7,0x80000007u ,
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8,6,9,6,10,4,11,4, 12,13,0, 14,2, 15,5,16,17,1 };
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redo(REDO,TestX28("../../cpp/raw/machineCsr/build/machineCsr",machineCsrRef, sizeof(machineCsrRef)/4).withRiscvRef()->noInstructionReadCheck()->run(10e4);)
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redo(REDO,TestX28("../../cpp/raw/machineCsr/build/machineCsr",machineCsrRef, sizeof(machineCsrRef)/4).withRiscvRef()->run(10e4);)
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#else
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uint32_t machineCsrRef[] = {1,11, 2,0x80000003u, 3,0x80000007u, 4,0x8000000bu, 5,6,7,0x80000007u ,
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8,6,9,6,10,4,11,4, 12,13, 14,2, 15,5,16,17,1 };
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redo(REDO,TestX28("../../cpp/raw/machineCsr/build/machineCsrCompressed",machineCsrRef, sizeof(machineCsrRef)/4).withRiscvRef()->noInstructionReadCheck()->run(10e4);)
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redo(REDO,TestX28("../../cpp/raw/machineCsr/build/machineCsrCompressed",machineCsrRef, sizeof(machineCsrRef)/4).withRiscvRef()->run(10e4);)
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#endif
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#endif
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// #ifdef MMU
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