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VexRiscv
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Default linux config is now without RVC 

Remove all linux usless CSR from the config
Remove verilator instruction fetch check
This commit is contained in:
Charles Papon 2019-04-11 01:18:15 +02:00
parent caa37a8028
commit ece1e73547
3 changed files with 57 additions and 27 deletions
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20
src/main/scala/vexriscv/demo/Linux.scala
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@ -40,13 +40,13 @@ cd VexRiscv
Run regressions => Run regressions =>
sbt "runMain vexriscv.demo.LinuxGen -r" sbt "runMain vexriscv.demo.LinuxGen -r"
cd src/test/cpp/regression cd src/test/cpp/regression
make run IBUS=CACHED DBUS=CACHED DEBUG_PLUGIN=STD DHRYSTONE=yes SUPERVISOR=yes CSR=yes COMPRESSED=yes LRSC=yes AMO=yes REDO=10 TRACE=no make run IBUS=CACHED DBUS=CACHED DEBUG_PLUGIN=STD DHRYSTONE=yes SUPERVISOR=yes CSR=yes COMPRESSED=no LRSC=yes AMO=yes REDO=10 TRACE=no
Run linux in simulation (Require the machime mode emulator compiled in SIM mode) => Run linux in simulation (Require the machime mode emulator compiled in SIM mode) =>
sbt "runMain vexriscv.demo.LinuxGen" sbt "runMain vexriscv.demo.LinuxGen"
cd src/test/cpp/regression cd src/test/cpp/regression
export BUILDROOT=/home/miaou/pro/riscv/buildrootSpinal export BUILDROOT=/home/miaou/pro/riscv/buildrootSpinal
make run IBUS=CACHED DBUS=CACHED DEBUG_PLUGIN=STD SUPERVISOR=yes CSR=yes COMPRESSED=yes LRSC=yes AMO=yes REDO=0 DHRYSTONE=no LINUX_SOC=yes EMULATOR=../../../main/c/emulator/build/emulator.bin VMLINUX=$BUILDROOT/output/images/Image DTB=$BUILDROOT/board/spinal/vexriscv_sim/rv32.dtb RAMDISK=$BUILDROOT/output/images/rootfs.cpio TRACE=no FLOW_INFO=no make run IBUS=CACHED DBUS=CACHED DEBUG_PLUGIN=STD SUPERVISOR=yes CSR=yes COMPRESSED=no LRSC=yes AMO=yes REDO=0 DHRYSTONE=no LINUX_SOC=yes EMULATOR=../../../main/c/emulator/build/emulator.bin VMLINUX=$BUILDROOT/output/images/Image DTB=$BUILDROOT/board/spinal/vexriscv_sim/rv32.dtb RAMDISK=$BUILDROOT/output/images/rootfs.cpio TRACE=no FLOW_INFO=no
Run linux with QEMU (Require the machime mode emulator compiled in QEMU mode) Run linux with QEMU (Require the machime mode emulator compiled in QEMU mode)
export BUILDROOT=/home/miaou/pro/riscv/buildrootSpinal export BUILDROOT=/home/miaou/pro/riscv/buildrootSpinal
@ -114,6 +114,12 @@ RAMDISK=/home/miaou/pro/riscv/buildrootSpinal/output/images/rootfs.cpio TRACE=no
make run IBUS=CACHED DBUS=CACHED DEBUG_PLUGIN=STD SUPERVISOR=yes CSR=yes COMPRESSED=yes LRSC=yes AMO=yes REDO=0 DHRYSTONE=no LINUX_SOC=yes DEBUG_PLUGIN_EXTERNAL=yes make run IBUS=CACHED DBUS=CACHED DEBUG_PLUGIN=STD SUPERVISOR=yes CSR=yes COMPRESSED=yes LRSC=yes AMO=yes REDO=0 DHRYSTONE=no LINUX_SOC=yes DEBUG_PLUGIN_EXTERNAL=yes
rm -rf cpio
mkdir cpio
cd cpio
ls | cpio -ov > ../rootfs.cpio
cpio -idv < ../rootfs.cpio
*/ */
@ -140,9 +146,9 @@ object LinuxGen {
//Uncomment the whole IBusCachedPlugin and comment IBusSimplePlugin if you want cached iBus config //Uncomment the whole IBusCachedPlugin and comment IBusSimplePlugin if you want cached iBus config
new IBusCachedPlugin( new IBusCachedPlugin(
resetVector = 0x80000000l, resetVector = 0x80000000l,
compressedGen = true, compressedGen = false,
prediction = NONE, prediction = NONE,
injectorStage = true, injectorStage = false,
config = InstructionCacheConfig( config = InstructionCacheConfig(
cacheSize = 4096*1, cacheSize = 4096*1,
bytePerLine = 32, bytePerLine = 32,
@ -232,7 +238,7 @@ object LinuxGen {
divUnrollFactor = 1 divUnrollFactor = 1
), ),
// new DivPlugin, // new DivPlugin,
new CsrPlugin(CsrPluginConfig.linux(0x80000020l).copy(ebreakGen = false)), new CsrPlugin(CsrPluginConfig.linuxMinimal(0x80000020l).copy(ebreakGen = false)),
// new CsrPlugin(//CsrPluginConfig.all2(0x80000020l).copy(ebreakGen = true)/* // new CsrPlugin(//CsrPluginConfig.all2(0x80000020l).copy(ebreakGen = true)/*
// CsrPluginConfig( // CsrPluginConfig(
// catchIllegalAccess = false, // catchIllegalAccess = false,
@ -398,7 +404,7 @@ object LinuxSyntesisBench extends App{
SpinalConfig(inlineRom=true).generateVerilog(new VexRiscv(LinuxGen.configFull(litex = false, withMmu = true)).setDefinitionName(getRtlPath().split("\\.").head)) SpinalConfig(inlineRom=true).generateVerilog(new VexRiscv(LinuxGen.configFull(litex = false, withMmu = true)).setDefinitionName(getRtlPath().split("\\.").head))
} }
val rtls = List(withoutMmu, withMmu) val rtls = List(/*withoutMmu, */withMmu)
// val rtls = List(smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache) // val rtls = List(smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache)
// val rtls = List(smallAndProductive, smallAndProductiveWithICache, fullNoMmuMaxPerf, fullNoMmu, full) // val rtls = List(smallAndProductive, smallAndProductiveWithICache, fullNoMmuMaxPerf, fullNoMmu, full)
// val rtls = List(fullNoMmu) // val rtls = List(fullNoMmu)
@ -408,7 +414,7 @@ object LinuxSyntesisBench extends App{
) ++ AlteraStdTargets( ) ++ AlteraStdTargets(
quartusCycloneIVPath = "/media/miaou/HD/linux/intelFPGA_lite/18.1/quartus/bin", quartusCycloneIVPath = "/media/miaou/HD/linux/intelFPGA_lite/18.1/quartus/bin",
quartusCycloneVPath = "/media/miaou/HD/linux/intelFPGA_lite/18.1/quartus/bin" quartusCycloneVPath = "/media/miaou/HD/linux/intelFPGA_lite/18.1/quartus/bin"
) ++ IcestormStdTargets().take(1) ) //++ IcestormStdTargets().take(1)
Bench(rtls, targets, "/media/miaou/HD/linux/tmp") Bench(rtls, targets, "/media/miaou/HD/linux/tmp")
} }

41
src/main/scala/vexriscv/plugin/CsrPlugin.scala
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@ -78,7 +78,46 @@ object CsrPluginConfig{
def all : CsrPluginConfig = all(0x00000020l) def all : CsrPluginConfig = all(0x00000020l)
def small : CsrPluginConfig = small(0x00000020l) def small : CsrPluginConfig = small(0x00000020l)
def smallest : CsrPluginConfig = smallest(0x00000020l) def smallest : CsrPluginConfig = smallest(0x00000020l)
def linux(mtVecInit : BigInt) = CsrPluginConfig( def linuxMinimal(mtVecInit : BigInt) = CsrPluginConfig(
catchIllegalAccess = true,
mvendorid = 1,
marchid = 2,
mimpid = 3,
mhartid = 0,
misaExtensionsInit = 0, //TODO
misaAccess = CsrAccess.NONE, //Read required by some regressions
mtvecAccess = CsrAccess.WRITE_ONLY, //Read required by some regressions
mtvecInit = mtVecInit,
mepcAccess = CsrAccess.READ_WRITE,
mscratchGen = true,
mcauseAccess = CsrAccess.READ_ONLY,
mbadaddrAccess = CsrAccess.READ_ONLY,
mcycleAccess = CsrAccess.NONE,
minstretAccess = CsrAccess.NONE,
ucycleAccess = CsrAccess.NONE,
wfiGenAsWait = true,
ecallGen = false,
xtvecModeGen = false,
noCsrAlu = false,
wfiGenAsNop = false,
ebreakGen = true,
supervisorGen = true,
sscratchGen = true,
stvecAccess = CsrAccess.READ_WRITE,
sepcAccess = CsrAccess.READ_WRITE,
scauseAccess = CsrAccess.READ_WRITE,
sbadaddrAccess = CsrAccess.READ_WRITE,
scycleAccess = CsrAccess.NONE,
sinstretAccess = CsrAccess.NONE,
satpAccess = CsrAccess.NONE, //Implemented into the MMU plugin
medelegAccess = CsrAccess.WRITE_ONLY,
midelegAccess = CsrAccess.WRITE_ONLY,
pipelineCsrRead = false,
deterministicInteruptionEntry = false
)
def linuxFull(mtVecInit : BigInt) = CsrPluginConfig(
catchIllegalAccess = true, catchIllegalAccess = true,
mvendorid = 1, mvendorid = 1,
marchid = 2, marchid = 2,

23
src/test/cpp/regression/main.cpp
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@ -1093,7 +1093,6 @@ public:
uint32_t seed; uint32_t seed;
bool withInstructionReadCheck = true;
Workspace* setIStall(bool enable) { iStall = enable; return this; } Workspace* setIStall(bool enable) { iStall = enable; return this; }
Workspace* setDStall(bool enable) { dStall = enable; return this; } Workspace* setDStall(bool enable) { dStall = enable; return this; }
@ -1402,9 +1401,9 @@ public:
virtual void pass(){ throw success();} virtual void pass(){ throw success();}
virtual void fail(){ throw std::exception();} virtual void fail(){ throw std::exception();}
virtual void fillSimELements(); virtual void fillSimELements();
Workspace* noInstructionReadCheck(){withInstructionReadCheck = false; return this;}
void dump(int i){ void dump(int i){
#ifdef TRACE #ifdef TRACE
if(i == TRACE_START) cout << "START TRACE" << endl;
if(i >= TRACE_START) tfp->dump(i); if(i >= TRACE_START) tfp->dump(i);
#endif #endif
} }
@ -1513,7 +1512,7 @@ public:
currentTime = i; currentTime = i;
#ifdef FLOW_INFO #ifdef FLOW_INFO
if(i % 100000 == 0) cout << "PROGRESS TRACE_START=" << i << endl; if(i % 2000000 == 0) cout << "PROGRESS TRACE_START=" << i << endl;
#endif #endif
@ -1604,17 +1603,6 @@ public:
dump(i + 1); dump(i + 1);
#ifndef COMPRESSED
if(withInstructionReadCheck){
if(top->VexRiscv->decode_arbitration_isValid && !top->VexRiscv->decode_arbitration_haltItself && !top->VexRiscv->decode_arbitration_flushAll){
uint32_t expectedData;
bool dummy;
iBusAccess(top->VexRiscv->decode_PC, &expectedData, &dummy);
assertEq(top->VexRiscv->decode_INSTRUCTION,expectedData);
}
}
#endif
checks(); checks();
//top->eval(); //top->eval();
top->clk = 1; top->clk = 1;
@ -2808,7 +2796,6 @@ public:
loadHex("../../resources/hex/" + name + ".elf.hex"); loadHex("../../resources/hex/" + name + ".elf.hex");
out32.open (name + ".out32"); out32.open (name + ".out32");
this->name = name; this->name = name;
if(name == "I-FENCE.I-01") withInstructionReadCheck = false;
} }
@ -3018,7 +3005,6 @@ public:
DebugPluginTest() : WorkspaceRegression("DebugPluginTest") { DebugPluginTest() : WorkspaceRegression("DebugPluginTest") {
loadHex("../../resources/hex/debugPlugin.hex"); loadHex("../../resources/hex/debugPlugin.hex");
pthread_create(&clientThreadId, NULL, &clientThreadWrapper, this); pthread_create(&clientThreadId, NULL, &clientThreadWrapper, this);
noInstructionReadCheck();
} }
virtual ~DebugPluginTest(){ virtual ~DebugPluginTest(){
@ -3526,7 +3512,6 @@ int main(int argc, char **argv, char **env) {
w.loadHex(RUN_HEX); w.loadHex(RUN_HEX);
w.withRiscvRef(); w.withRiscvRef();
#endif #endif
w.noInstructionReadCheck();
//w.setIStall(false); //w.setIStall(false);
//w.setDStall(false); //w.setDStall(false);
@ -3604,11 +3589,11 @@ int main(int argc, char **argv, char **env) {
#ifndef COMPRESSED #ifndef COMPRESSED
uint32_t machineCsrRef[] = {1,11, 2,0x80000003u, 3,0x80000007u, 4,0x8000000bu, 5,6,7,0x80000007u , uint32_t machineCsrRef[] = {1,11, 2,0x80000003u, 3,0x80000007u, 4,0x8000000bu, 5,6,7,0x80000007u ,
8,6,9,6,10,4,11,4, 12,13,0, 14,2, 15,5,16,17,1 }; 8,6,9,6,10,4,11,4, 12,13,0, 14,2, 15,5,16,17,1 };
redo(REDO,TestX28("../../cpp/raw/machineCsr/build/machineCsr",machineCsrRef, sizeof(machineCsrRef)/4).withRiscvRef()->noInstructionReadCheck()->run(10e4);) redo(REDO,TestX28("../../cpp/raw/machineCsr/build/machineCsr",machineCsrRef, sizeof(machineCsrRef)/4).withRiscvRef()->run(10e4);)
#else #else
uint32_t machineCsrRef[] = {1,11, 2,0x80000003u, 3,0x80000007u, 4,0x8000000bu, 5,6,7,0x80000007u , uint32_t machineCsrRef[] = {1,11, 2,0x80000003u, 3,0x80000007u, 4,0x8000000bu, 5,6,7,0x80000007u ,
8,6,9,6,10,4,11,4, 12,13, 14,2, 15,5,16,17,1 }; 8,6,9,6,10,4,11,4, 12,13, 14,2, 15,5,16,17,1 };
redo(REDO,TestX28("../../cpp/raw/machineCsr/build/machineCsrCompressed",machineCsrRef, sizeof(machineCsrRef)/4).withRiscvRef()->noInstructionReadCheck()->run(10e4);) redo(REDO,TestX28("../../cpp/raw/machineCsr/build/machineCsrCompressed",machineCsrRef, sizeof(machineCsrRef)/4).withRiscvRef()->run(10e4);)
#endif #endif
#endif #endif
// #ifdef MMU // #ifdef MMU