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more pipelineing in Litex SMP cluster interconnect

This commit is contained in:
Dolu1990 2020-05-06 17:06:45 +02:00
parent 8043feebd5
commit ed4a89e4af
1 changed files with 15 additions and 8 deletions
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23
src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala
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@ -180,10 +180,11 @@ case class BmbToLiteDram(bmbParameter : BmbParameter,
io.output.cmd.we := cmdFork.isWrite io.output.cmd.we := cmdFork.isWrite
if(bmbParameter.canWrite) { if(bmbParameter.canWrite) {
val fifo = dataFork.throwWhen(dataFork.isRead).queue(wdataFifoSize) val wData = Stream(LiteDramNativeWData(liteDramParameter))
io.output.wdata.arbitrationFrom(fifo) wData.arbitrationFrom(dataFork.throwWhen(dataFork.isRead))
io.output.wdata.data := fifo.data wData.data := dataFork.data
io.output.wdata.we := fifo.mask wData.we := dataFork.mask
io.output.wdata << wData.queue(wdataFifoSize)
} else { } else {
dataFork.ready := True dataFork.ready := True
io.output.wdata.valid := False io.output.wdata.valid := False
@ -305,7 +306,13 @@ case class VexRiscvLitexSmpCluster(p : VexRiscvLitexSmpClusterParameter,
pendingMax = 15 pendingMax = 15
) )
iBusDecoder.io.input << iBusArbiter.io.output iBusDecoder.io.input << iBusArbiter.io.output
val iMemBridge = io.iMem.fromBmb(iBusDecoder.io.outputs(1), wdataFifoSize = 0, rdataFifoSize = 32)
val iMem = LiteDramNative(p.liteDram)
val iMemBridge = iMem.fromBmb(iBusDecoder.io.outputs(1), wdataFifoSize = 0, rdataFifoSize = 32)
iMem.cmd >-> io.iMem.cmd
iMem.wdata >> io.iMem.wdata
iMem.rdata << io.iMem.rdata
val peripheralAccessLength = Math.max(iBusDecoder.io.outputs(0).p.lengthWidth, dBusDecoder.io.outputs(0).p.lengthWidth) val peripheralAccessLength = Math.max(iBusDecoder.io.outputs(0).p.lengthWidth, dBusDecoder.io.outputs(0).p.lengthWidth)
val peripheralArbiter = BmbArbiter( val peripheralArbiter = BmbArbiter(
@ -316,7 +323,7 @@ case class VexRiscvLitexSmpCluster(p : VexRiscvLitexSmpClusterParameter,
peripheralArbiter.io.inputs(0) << iBusDecoder.io.outputs(0).resize(dataWidth = 32).pipelined(cmdHalfRate = true, rspValid = true) peripheralArbiter.io.inputs(0) << iBusDecoder.io.outputs(0).resize(dataWidth = 32).pipelined(cmdHalfRate = true, rspValid = true)
peripheralArbiter.io.inputs(1) << dBusDecoder.io.outputs(0).resize(dataWidth = 32).pipelined(cmdHalfRate = true, rspValid = true) peripheralArbiter.io.inputs(1) << dBusDecoder.io.outputs(0).resize(dataWidth = 32).pipelined(cmdHalfRate = true, rspValid = true)
val peripheralWishbone = peripheralArbiter.io.output.toWishbone() val peripheralWishbone = peripheralArbiter.io.output.pipelined(cmdValid = true).toWishbone()
io.peripheral << peripheralWishbone io.peripheral << peripheralWishbone
} }
@ -343,8 +350,8 @@ object VexRiscvLitexSmpClusterGen extends App {
debugClockDomain = ClockDomain.current.copy(reset = Bool().setName("debugResetIn")) debugClockDomain = ClockDomain.current.copy(reset = Bool().setName("debugResetIn"))
) )
// SpinalVerilog(Bench.compressIo(dutGen)) SpinalVerilog(Bench.compressIo(dutGen))
SpinalVerilog(dutGen) // SpinalVerilog(dutGen)
} }