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Cleaning, better jtag perf

This commit is contained in:
Charles Papon 2017-06-18 16:10:27 +02:00
parent a94343b98a
commit edf1b4ed5a
5 changed files with 186 additions and 84 deletions
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4
src/main/scala/VexRiscv/demo/Briey.scala
View File

@ -244,7 +244,9 @@ class Briey(config: BrieyConfig) extends Component{
new SrcPlugin(
separatedAddSub = false
),
new LightShifterPlugin,
new FullBarrielShifterPlugin,
new MulPlugin,
new DivPlugin,
new HazardSimplePlugin(
bypassExecute = true,
bypassMemory = true,

74
src/test/cpp/briey/main.cpp
View File

@ -164,7 +164,7 @@ public:
struct sockaddr_in serverAddr;
struct sockaddr_storage serverStorage;
socklen_t addr_size;
uint64_t period;
uint64_t tooglePeriod;
// char buffer[1024];
Jtag(CData *tms, CData *tdi, CData *tdo, CData* tck,uint64_t period){
@ -172,7 +172,7 @@ public:
this->tdi = tdi;
this->tdo = tdo;
this->tck = tck;
this->period = period;
this->tooglePeriod = period/2;
*tms = 0;
*tdi = 0;
*tdo = 0;
@ -192,6 +192,15 @@ public:
cruft */
sizeof(int)); /* length of option value */
/*int a = 0xFFF;
if (setsockopt(serverSocket, SOL_SOCKET, SO_RCVBUF, &a, sizeof(int)) == -1) {
fprintf(stderr, "Error setting socket opts: %s\n", strerror(errno));
}
a = 0xFFFFFF;
if (setsockopt(serverSocket, SOL_SOCKET, SO_SNDBUF, &a, sizeof(int)) == -1) {
fprintf(stderr, "Error setting socket opts: %s\n", strerror(errno));
}*/
SetSocketBlockingEnabled(serverSocket,0);
@ -232,27 +241,51 @@ public:
}
uint32_t selfSleep = 0;
uint32_t checkNewConnectionsTimer = 0;
uint8_t rxBuffer[100];
int32_t rxBufferSize = 0;
int32_t rxBufferRemaining = 0;
virtual void tick(){
checkNewConnectionsTimer++;
if(checkNewConnectionsTimer == 5000){
checkNewConnectionsTimer = 0;
int newclientHandle = accept(serverSocket, (struct sockaddr *) &serverStorage, &addr_size);
if(newclientHandle != -1){
if(clientHandle != -1){
connectionReset();
}
clientHandle = newclientHandle;
printf("CONNECTED\n");
}
else{
if(clientHandle == -1)
selfSleep = 1000;
}
}
if(selfSleep)
selfSleep--;
else{
if(clientHandle == -1){
clientHandle = accept(serverSocket, (struct sockaddr *) &serverStorage, &addr_size);
if(clientHandle != -1)
printf("CONNECTED\n");
else
selfSleep = 1000;
}
if(clientHandle != -1){
uint8_t buffer;
int n;
if(rxBufferRemaining == 0){
if(ioctl(clientHandle,FIONREAD,&n) != 0)
connectionReset();
else if(n >= 1){
switch(read(clientHandle,&buffer,1)){
case 0: break;
case 1:
rxBufferSize = read(clientHandle,&rxBuffer,100);
if(rxBufferSize < 0){
connectionReset();
}else {
rxBufferRemaining = rxBufferSize;
}
}else {
selfSleep = 30;
}
}
if(rxBufferRemaining != 0){
uint8_t buffer = rxBuffer[rxBufferSize - (rxBufferRemaining--)];
*tms = (buffer & 1) != 0;
*tdi = (buffer & 2) != 0;
*tck = (buffer & 8) != 0;
@ -265,17 +298,10 @@ public:
// printf("\n");
}
break;
default:
connectionReset();
break;
}
}else{
selfSleep = 10;
}
}
}
schedule(period);
schedule(tooglePeriod);
}
};
@ -530,9 +556,9 @@ public:
if(!opened)
cout << "SDRAM : write in closed bank" << endl;
uint32_t addr = byteId + (column + openedRow * config->colSize) * config->byteCount;
//printf("SDRAM : Write A=%08x D=%02x\n",addr,data);
this->data[addr] = data;
//printf("SDRAM : Write A=%08x D=%02x\n",addr,data);
}
CData read(uint32_t column, CData byteId){
@ -705,7 +731,7 @@ public:
ClockDomain *axiClk = new ClockDomain(&top->io_axiClk,NULL,20000,100000);
ClockDomain *vgaClk = new ClockDomain(&top->io_vgaClk,NULL,40000,100000);
AsyncReset *asyncReset = new AsyncReset(&top->io_asyncReset,50000);
Jtag *jtag = new Jtag(&top->io_jtag_tms,&top->io_jtag_tdi,&top->io_jtag_tdo,&top->io_jtag_tck,60000);
Jtag *jtag = new Jtag(&top->io_jtag_tms,&top->io_jtag_tdi,&top->io_jtag_tdo,&top->io_jtag_tck,80000);
UartRx *uartRx = new UartRx(&top->io_uart_txd,(50000000/8/115200)*8*axiClk->tooglePeriod*2);
timeProcesses.push_back(axiClk);
timeProcesses.push_back(vgaClk);
@ -716,8 +742,8 @@ public:
SdramConfig *sdramConfig = new SdramConfig(
2, //byteCount
4, //bankCount
13, //rowSize
10 //colSize
1 << 13, //rowSize
1 << 10 //colSize
);
SdramIo *sdramIo = new SdramIo();
sdramIo->BA = &top->io_sdram_BA ;

2
src/test/cpp/briey/makefile
View File

@ -9,7 +9,7 @@ ifeq ($(TRACE),yes)
ADDCFLAGS += -CFLAGS -DTRACE
endif
ifeq ($(DEBUG),yes)
ADDCFLAGS += -CFLAGS "-g -O0"
ADDCFLAGS += -CFLAGS "-g3 -O0"
endif
ifneq ($(DEBUG),yes)
ADDCFLAGS += -CFLAGS "-O3"

20
src/test/cpp/briey/makefile~
View File

@ -1,22 +1,34 @@
DEBUG?=no
TRACE?=no
PRINT_PERF?=no
TRACE_START=0
ADDCFLAGS += -CFLAGS -pthread
ifeq ($(TRACE),yes)
VERILATOR_ARGS += --trace
ADDCFLAGS += -CFLAGS -DTRACE
endif
ifeq ($(DEBUG),yes)
ADDCFLAGS += -CFLAGS "-g3 -O0"
endif
ifneq ($(DEBUG),yes)
ADDCFLAGS += -CFLAGS "-O3"
endif
ifeq ($(PRINT_PERF),yes)
ADDCFLAGS += -CFLAGS -DPRINT_PERF
endif
ADDCFLAGS += -CFLAGS -DTRACE_START=${TRACE_START}
all: clean compile
run: compile
./obj_dir/VBriey
verilate:
verilator -cc ../../../../Briey.v -O3 -CFLAGS -std=c++11 -LDFLAGS -pthread ${ADDCFLAGS} --gdbbt ${VERILATOR_ARGS} -Wno-WIDTH --x-assign unique --exe main.cpp
verilator -cc ../../../../Briey.v -CFLAGS -std=c++11 ${ADDCFLAGS} --gdbbt ${VERILATOR_ARGS} -Wno-WIDTH --x-assign unique --exe main.cpp
compile: verilate
make -j -C obj_dir/ -f VBriey.mk VBriey

142
src/test/cpp/briey/wip.gtkw
View File

@ -1,60 +1,122 @@
[*]
[*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI
[*] Sat Jun 10 13:47:38 2017
[*] Sat Jun 17 11:02:57 2017
[*]
[dumpfile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/briey/Briey.vcd"
[dumpfile_mtime] "Sat Jun 10 13:46:48 2017"
[dumpfile_size] 485915260
[dumpfile_mtime] "Sat Jun 17 10:33:51 2017"
[dumpfile_size] 3778117632
[savefile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/briey/wip.gtkw"
[timestart] 0
[timestart] 123264434700
[size] 1776 953
[pos] -775 -353
*-18.000000 260000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[pos] -1 -1
*-17.000000 123264547400 106440000000 123264547400 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] TOP.
[treeopen] TOP.Briey.
[treeopen] TOP.Briey.axi_uartCtrl.
[sst_width] 269
[signals_width] 310
[treeopen] TOP.Briey.axi_sdramCtrl.
[sst_width] 507
[signals_width] 567
[sst_expanded] 1
[sst_vpaned_height] 503
@28
TOP.Briey.axi_uartCtrl.io_axiClk
@22
TOP.Briey.axi_uartCtrl.io_apb_PADDR[3:0]
@28
TOP.Briey.axi_uartCtrl.io_apb_PENABLE
@22
TOP.Briey.axi_uartCtrl.io_apb_PRDATA[31:0]
@28
TOP.Briey.axi_uartCtrl.io_apb_PREADY
TOP.Briey.axi_uartCtrl.io_apb_PSEL[0]
@22
TOP.Briey.axi_uartCtrl.io_apb_PWDATA[31:0]
@28
TOP.Briey.axi_uartCtrl.io_apb_PWRITE
@24
TOP.Briey.axi_uartCtrl.uartCtrl_1.io_config_clockDivider[19:0]
@28
TOP.Briey.axi_uartCtrl.uartCtrl_1.io_config_frame_dataLength[2:0]
TOP.Briey.axi_uartCtrl.uartCtrl_1.io_config_frame_parity[1:0]
TOP.Briey.axi_uartCtrl.uartCtrl_1.io_config_frame_stop[0]
TOP.Briey.axi_uartCtrl.uartCtrl_1.io_uart_txd
@22
TOP.Briey.axi_core_cpu.DebugPlugin_busReadDataReg[31:0]
@28
TOP.Briey.axi_core_cpu.DebugPlugin_firstCycle
TOP.Briey.axi_core_cpu.DebugPlugin_haltIt
TOP.Briey.axi_core_cpu.DebugPlugin_haltedByBreak
TOP.Briey.axi_core_cpu.DebugPlugin_insertDecodeInstruction
TOP.Briey.axi_core_cpu.DebugPlugin_isPipActive
TOP.Briey.axi_core_cpu.DebugPlugin_isPipBusy
TOP.Briey.axi_core_cpu.DebugPlugin_resetIt
TOP.Briey.axi_core_cpu.DebugPlugin_stepIt
TOP.Briey.axi_core_cpu.decode_IS_EBREAK
TOP.Briey.axi_core_cpu.timerInterrupt
TOP.Briey.axi_timerCtrl.timerA.io_tick
TOP.Briey.axi_timerCtrl.timerA.io_clear
TOP.Briey.axi_timerCtrl.timerA.io_full
@22
TOP.Briey.axi_timerCtrl.timerA.io_limit[31:0]
@28
TOP.Briey.axi_timerCtrl.timerA.io_tick
@22
TOP.Briey.axi_timerCtrl.timerA.io_value[31:0]
@28
TOP.Briey.axi_timerCtrl.prescaler_1.io_clear
@22
TOP.Briey.axi_timerCtrl.prescaler_1.io_limit[15:0]
@28
TOP.Briey.axi_timerCtrl.prescaler_1.io_overflow
@22
TOP.Briey.axi_timerCtrl.io_apb_PADDR[7:0]
@28
TOP.Briey.axi_timerCtrl.io_apb_PENABLE
@22
TOP.Briey.axi_timerCtrl.io_apb_PRDATA[31:0]
@28
TOP.Briey.axi_timerCtrl.io_apb_PREADY
TOP.Briey.axi_timerCtrl.io_apb_PSEL[0]
@22
TOP.Briey.axi_timerCtrl.io_apb_PWDATA[31:0]
@28
TOP.Briey.axi_timerCtrl.io_apb_PWRITE
TOP.Briey.axi_timerCtrl.timerABridge_busClearing
TOP.Briey.axi_timerCtrl.timerABridge_clearsEnable[0]
TOP.Briey.axi_timerCtrl.timerABridge_ticksEnable[1:0]
TOP.Briey.axi_core_cpu.writeBack_arbitration_isValid
@22
TOP.Briey.axi_core_cpu.writeBack_PC[31:0]
TOP.Briey.axi_core_cpu.writeBack_RegFilePlugin_regFileWrite_payload_address[4:0]
TOP.Briey.axi_core_cpu.writeBack_RegFilePlugin_regFileWrite_payload_data[31:0]
@28
TOP.Briey.axi_core_cpu.writeBack_RegFilePlugin_regFileWrite_valid
@22
TOP.Briey.axi_core_cpu.writeBack_INSTRUCTION[31:0]
TOP.Briey.axi_core_cpu.decode_INSTRUCTION[31:0]
TOP.Briey.axi_core_cpu.decode_PC[31:0]
@28
TOP.Briey.axi_core_cpu.decode_arbitration_isValid
@22
TOP.Briey.axi_core_cpu.decode_PC[31:0]
@23
TOP.Briey.axi_core_cpu.decode_INSTRUCTION[31:0]
TOP.Briey.axi_core_cpu.iBus_cmd_payload_address[31:0]
@28
TOP.Briey.axi_core_cpu.iBus_cmd_ready
TOP.Briey.axi_core_cpu.iBus_cmd_valid
@22
TOP.Briey.axi_core_cpu.iBus_rsp_payload_data[31:0]
@28
TOP.Briey.axi_core_cpu.iBus_rsp_valid
@22
TOP.Briey.axi_sdramCtrl.io_axi_arw_payload_addr[25:0]
@28
TOP.Briey.axi_sdramCtrl.io_axi_arw_payload_burst[1:0]
@22
TOP.Briey.axi_sdramCtrl.io_axi_arw_payload_id[3:0]
TOP.Briey.axi_sdramCtrl.io_axi_arw_payload_len[7:0]
@28
TOP.Briey.axi_sdramCtrl.io_axi_arw_payload_size[2:0]
TOP.Briey.axi_sdramCtrl.io_axi_arw_payload_write
TOP.Briey.axi_sdramCtrl.io_axi_arw_ready
TOP.Briey.axi_sdramCtrl.io_axi_arw_valid
@22
TOP.Briey.axi_sdramCtrl.io_axi_r_payload_data[31:0]
TOP.Briey.axi_sdramCtrl.io_axi_r_payload_id[3:0]
@28
TOP.Briey.axi_sdramCtrl.io_axi_r_payload_last
TOP.Briey.axi_sdramCtrl.io_axi_r_ready
TOP.Briey.axi_sdramCtrl.io_axi_r_valid
@22
TOP.Briey.axi_sdramCtrl.ctrl.io_bus_cmd_payload_address[24:0]
TOP.Briey.axi_sdramCtrl.ctrl.io_bus_cmd_payload_context_id[3:0]
@28
TOP.Briey.axi_sdramCtrl.ctrl.io_bus_cmd_payload_context_last
@22
TOP.Briey.axi_sdramCtrl.ctrl.io_bus_cmd_payload_data[15:0]
@28
TOP.Briey.axi_sdramCtrl.ctrl.io_bus_cmd_payload_mask[1:0]
TOP.Briey.axi_sdramCtrl.ctrl.io_bus_cmd_payload_write
TOP.Briey.axi_sdramCtrl.ctrl.io_bus_cmd_ready
@29
TOP.Briey.axi_sdramCtrl.ctrl.io_bus_cmd_valid
@22
TOP.Briey.axi_sdramCtrl.ctrl.io_bus_rsp_payload_context_id[3:0]
@28
TOP.Briey.axi_sdramCtrl.ctrl.io_bus_rsp_payload_context_last
@22
TOP.Briey.axi_sdramCtrl.ctrl.io_bus_rsp_payload_data[15:0]
@28
TOP.Briey.axi_sdramCtrl.ctrl.io_bus_rsp_ready
TOP.Briey.axi_sdramCtrl.ctrl.io_bus_rsp_valid
[pattern_trace] 1
[pattern_trace] 0