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VexRiscv
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fetcher force PC LSB to be zero

This commit is contained in:
Dolu1990 2018-10-12 12:02:52 +02:00
parent 0b8f6f6ed4
commit eea92154ae
1 changed files with 3 additions and 0 deletions
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3
src/main/scala/vexriscv/plugin/Fetcher.scala
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@ -155,9 +155,12 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
pcReg := pc pcReg := pc
} }
pc(0) := False
if(!pipeline(RVC_GEN)) pc(1) := False
preOutput.valid := RegNext(True) init (False) preOutput.valid := RegNext(True) init (False)
preOutput.payload := pc preOutput.payload := pc
} }
val decodePc = ifGen(decodePcGen)(new Area { val decodePc = ifGen(decodePcGen)(new Area {