fetcher force PC LSB to be zero

2018-10-12 12:02:52 +02:00 · 2018-10-12 12:02:52 +02:00 · eea92154ae
parent 0b8f6f6ed4
commit eea92154ae
1 changed files with 3 additions and 0 deletions
--- a/src/main/scala/vexriscv/plugin/Fetcher.scala
+++ b/src/main/scala/vexriscv/plugin/Fetcher.scala
@ -155,9 +155,12 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
        pcReg := pc
      }

+      pc(0) := False
+      if(!pipeline(RVC_GEN)) pc(1) := False

      preOutput.valid := RegNext(True) init (False)
      preOutput.payload := pc
+
    }

    val decodePc = ifGen(decodePcGen)(new Area {