Add MachineCsr.mbadaddr logics
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349d600182
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@ -74,8 +74,9 @@ class BranchPlugin(earlyBranch : Boolean,
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if (catchUnalignedException) {
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val exceptionService = pipeline.service(classOf[ExceptionService])
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branchExceptionPort = exceptionService.newExceptionPort(if (earlyBranch) pipeline.execute else pipeline.memory)
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if (prediction != NONE)
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if (prediction != NONE) {
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predictionExceptionPort = exceptionService.newExceptionPort(pipeline.decode)
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}
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}
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}
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@ -132,6 +133,7 @@ class BranchPlugin(earlyBranch : Boolean,
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if(catchUnalignedException) {
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branchExceptionPort.valid := arbitration.isValid && input(BRANCH_DO) && jumpInterface.payload(1 downto 0) =/= 0
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branchExceptionPort.code := 0
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branchExceptionPort.badAddr := jumpInterface.payload
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}
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}
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}
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@ -182,6 +184,7 @@ class BranchPlugin(earlyBranch : Boolean,
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if(catchUnalignedException) {
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predictionExceptionPort.valid := input(PREDICTION_HAD_BRANCHED) && arbitration.isValid && predictionJumpInterface.payload(1 downto 0) =/= 0
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predictionExceptionPort.code := 0
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predictionExceptionPort.badAddr := predictionJumpInterface.payload
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}
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}
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@ -237,6 +240,7 @@ class BranchPlugin(earlyBranch : Boolean,
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if(catchUnalignedException) {
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branchExceptionPort.valid := arbitration.isValid && input(BRANCH_DO) && jumpInterface.payload(1 downto 0) =/= 0
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branchExceptionPort.code := 0
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branchExceptionPort.badAddr := jumpInterface.payload
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}
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}
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@ -103,6 +103,7 @@ class DBusSimplePlugin(catchUnalignedException : Boolean) extends Plugin[VexRisc
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if(catchUnalignedException){
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executeExceptionPort.code := (dCmd.wr ? U(6) | U(4)).resized
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executeExceptionPort.badAddr := dCmd.address
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executeExceptionPort.valid := (arbitration.isValid && input(MEMORY_ENABLE)
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&& ((dCmd.size === 2 && dCmd.address(1 downto 0) =/= 0) || (dCmd.size === 1 && dCmd.address(0 downto 0) =/= 0)))
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}
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@ -125,6 +125,7 @@ class DecoderSimplePlugin(catchIllegalInstruction : Boolean) extends Plugin[VexR
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if(catchIllegalInstruction){
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decodeExceptionPort.valid := arbitration.isValid && !input(LEGAL_INSTRUCTION)
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decodeExceptionPort.code := 2
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decodeExceptionPort.badAddr.assignDontCare()
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}
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}
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@ -311,6 +311,9 @@ class MachineCsr(config : MachineCsrConfig) extends Plugin[VexRiscv] with Except
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True -> ((mip.MEIP && mie.MEIE) ? U(11) | ((mip.MSIP && mie.MSIE) ? U(3) | U(7))),
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False -> (if(exceptionPortCtrl != null) exceptionPortCtrl.exceptionContext.code else U(0))
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)
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when(exception){
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mbadaddr := exceptionPortCtrl.exceptionContext.badAddr
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}
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}
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@ -15,6 +15,7 @@ trait DecoderService{
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case class ExceptionCause() extends Bundle{
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val code = UInt(4 bits)
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val badAddr = UInt(32 bits)
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}
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trait ExceptionService{
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@ -99,7 +99,42 @@ object TopLevel {
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)
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)
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// config.plugins ++= List(
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// new PcManagerSimplePlugin(0x00000000l, false),
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// new IBusSimplePlugin(
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// interfaceKeepData = true
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// ),
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// new DecoderSimplePlugin(
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// catchIllegalInstruction = false
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// ),
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// new RegFilePlugin(
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// regFileReadyKind = Plugin.SYNC,
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// zeroBoot = false
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// ),
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// new IntAluPlugin,
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// new SrcPlugin,
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//// new FullBarrielShifterPlugin,
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// new LightShifterPlugin,
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// new DBusSimplePlugin(
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// catchUnalignedException = false
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// ),
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//// new HazardSimplePlugin(true, true, true, true),
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// // new HazardSimplePlugin(false, true, false, true),
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// new HazardSimplePlugin(false, false, false, false),
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//// new MulPlugin,
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//// new DivPlugin,
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//// new MachineCsr(csrConfig),
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// new BranchPlugin(
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// earlyBranch = false,
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// catchUnalignedException = false,
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// prediction = NONE
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// )
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// )
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val toplevel = new VexRiscv(config)
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// toplevel.service(classOf[DecoderSimplePlugin]).bench(toplevel)
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toplevel
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}
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}
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@ -608,6 +608,7 @@ int main(int argc, char **argv, char **env) {
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// Dhrystone("dhrystoneO3",false,false).run(0.05e6);
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Dhrystone("dhrystoneO3",true,true).run(1.1e6);
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Dhrystone("dhrystoneO3M",true,true).run(0.8e6);
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Dhrystone("dhrystoneO3",false,false).run(1.1e6);
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Dhrystone("dhrystoneO3M",false,false).run(0.8e6);
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// Dhrystone("dhrystoneO3ML",false,false).run(8e6);
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// Dhrystone("dhrystoneO3MLL",false,false).run(80e6);
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@ -2,7 +2,7 @@ TRACE=no
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TRACE_START=0
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CSR=yes
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DHRYSTONE=yes
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FREE_RTOS=yes
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FREE_RTOS=no
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REDO=10
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REF=no
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TRACE_WITH_TIME=no
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