Add MachineCsr.mbadaddr logics

src/main/scala/SpinalRiscv/Plugin/BranchPlugin.scala

@@ -74,10 +74,11 @@ class BranchPlugin(earlyBranch : Boolean,
     if (catchUnalignedException) {
       val exceptionService = pipeline.service(classOf[ExceptionService])
       branchExceptionPort = exceptionService.newExceptionPort(if (earlyBranch) pipeline.execute else pipeline.memory)
-      if (prediction != NONE)
+      if (prediction != NONE) {
         predictionExceptionPort = exceptionService.newExceptionPort(pipeline.decode)
       }
     }
+  }
 
   override def build(pipeline: VexRiscv): Unit = prediction match {
     case NONE => buildWithoutPrediction(pipeline)
@@ -132,6 +133,7 @@ class BranchPlugin(earlyBranch : Boolean,
       if(catchUnalignedException) {
         branchExceptionPort.valid := arbitration.isValid && input(BRANCH_DO) && jumpInterface.payload(1 downto 0) =/= 0
         branchExceptionPort.code := 0
+        branchExceptionPort.badAddr := jumpInterface.payload
       }
     }
   }
@@ -182,6 +184,7 @@ class BranchPlugin(earlyBranch : Boolean,
       if(catchUnalignedException) {
         predictionExceptionPort.valid := input(PREDICTION_HAD_BRANCHED) && arbitration.isValid && predictionJumpInterface.payload(1 downto 0) =/= 0
         predictionExceptionPort.code := 0
+        predictionExceptionPort.badAddr := predictionJumpInterface.payload
       }
     }
 
@@ -237,6 +240,7 @@ class BranchPlugin(earlyBranch : Boolean,
       if(catchUnalignedException) {
         branchExceptionPort.valid := arbitration.isValid && input(BRANCH_DO) && jumpInterface.payload(1 downto 0) =/= 0
         branchExceptionPort.code := 0
+        branchExceptionPort.badAddr := jumpInterface.payload
       }
     }
 

src/main/scala/SpinalRiscv/Plugin/DBusSimplePlugin.scala

@@ -103,6 +103,7 @@ class DBusSimplePlugin(catchUnalignedException : Boolean) extends Plugin[VexRisc
 
       if(catchUnalignedException){
         executeExceptionPort.code := (dCmd.wr ? U(6) | U(4)).resized
+        executeExceptionPort.badAddr := dCmd.address
         executeExceptionPort.valid := (arbitration.isValid && input(MEMORY_ENABLE)
           && ((dCmd.size === 2 && dCmd.address(1 downto 0) =/= 0) || (dCmd.size === 1 && dCmd.address(0 downto 0) =/= 0)))
       }

src/main/scala/SpinalRiscv/Plugin/DecoderSimplePlugin.scala

@@ -125,6 +125,7 @@ class DecoderSimplePlugin(catchIllegalInstruction : Boolean) extends Plugin[VexR
     if(catchIllegalInstruction){
       decodeExceptionPort.valid := arbitration.isValid && !input(LEGAL_INSTRUCTION)
       decodeExceptionPort.code := 2
+      decodeExceptionPort.badAddr.assignDontCare()
     }
   }
 

src/main/scala/SpinalRiscv/Plugin/MachineCsr.scala

@@ -311,6 +311,9 @@ class MachineCsr(config : MachineCsrConfig) extends Plugin[VexRiscv] with Except
           True  -> ((mip.MEIP && mie.MEIE) ? U(11) | ((mip.MSIP && mie.MSIE) ? U(3) | U(7))),
           False -> (if(exceptionPortCtrl != null) exceptionPortCtrl.exceptionContext.code else U(0))
         )
+        when(exception){
+          mbadaddr := exceptionPortCtrl.exceptionContext.badAddr
+        }
       }
 
 

src/main/scala/SpinalRiscv/Services.scala

@@ -15,6 +15,7 @@ trait DecoderService{
 
 case class ExceptionCause() extends Bundle{
   val code = UInt(4 bits)
+  val badAddr = UInt(32 bits)
 }
 
 trait ExceptionService{

src/main/scala/SpinalRiscv/TopLevel.scala

@@ -99,7 +99,42 @@ object TopLevel {
         )
       )
 
+//      config.plugins ++= List(
+//        new PcManagerSimplePlugin(0x00000000l, false),
+//        new IBusSimplePlugin(
+//          interfaceKeepData = true
+//        ),
+//        new DecoderSimplePlugin(
+//          catchIllegalInstruction = false
+//        ),
+//        new RegFilePlugin(
+//          regFileReadyKind = Plugin.SYNC,
+//          zeroBoot = false
+//        ),
+//        new IntAluPlugin,
+//        new SrcPlugin,
+////        new FullBarrielShifterPlugin,
+//        new LightShifterPlugin,
+//        new DBusSimplePlugin(
+//          catchUnalignedException = false
+//        ),
+////        new HazardSimplePlugin(true, true, true, true),
+//        //        new HazardSimplePlugin(false, true, false, true),
+//        new HazardSimplePlugin(false, false, false, false),
+////        new MulPlugin,
+////        new DivPlugin,
+////        new MachineCsr(csrConfig),
+//        new BranchPlugin(
+//          earlyBranch = false,
+//          catchUnalignedException = false,
+//          prediction = NONE
+//        )
+//      )
+
       val toplevel = new VexRiscv(config)
+
+//      toplevel.service(classOf[DecoderSimplePlugin]).bench(toplevel)
+
       toplevel
     }
   }

src/test/cpp/testA/main.cpp

@@ -608,6 +608,7 @@ int main(int argc, char **argv, char **env) {
 //		Dhrystone("dhrystoneO3",false,false).run(0.05e6);
 		Dhrystone("dhrystoneO3",true,true).run(1.1e6);
 		Dhrystone("dhrystoneO3M",true,true).run(0.8e6);
+		Dhrystone("dhrystoneO3",false,false).run(1.1e6);
 		Dhrystone("dhrystoneO3M",false,false).run(0.8e6);
 //		Dhrystone("dhrystoneO3ML",false,false).run(8e6);
 //		Dhrystone("dhrystoneO3MLL",false,false).run(80e6);

src/test/cpp/testA/makefile

@@ -2,7 +2,7 @@ TRACE=no
 TRACE_START=0
 CSR=yes
 DHRYSTONE=yes
-FREE_RTOS=yes
+FREE_RTOS=no
 REDO=10
 REF=no
 TRACE_WITH_TIME=no