Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Fix demo

This commit is contained in:
Dolu1990 2023-11-03 11:41:02 +01:00
parent e6998d1cb3
commit f1d64eccc8
1 changed files with 2 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/main/scala/vexriscv/demo/GenFullWithOfficialRiscvDebug.scala
View File

@ -9,7 +9,7 @@ import vexriscv.{VexRiscv, VexRiscvConfig, plugin}
/**
* This an example of VexRiscv configuration which can run the official RISC-V debug.
* You can for instance :
* - generate this VexRiscv
* - sbt "runMain vexriscv.demo.GenFullWithOfficialRiscvDebug"
* - cd src/test/cpp/regression
* - make IBUS=CACHED IBUS_DATA_WIDTH=64 COMPRESSED=no DBUS=CACHED DBUS_LOAD_DATA_WIDTH=64 DBUS_STORE_DATA_WIDTH=64 LRSC=yes AMO=yes DBUS_EXCLUSIVE=yes DBUS_INVALIDATE=yes MUL=yes DIV=yes SUPERVISOR=yes CSR=yes RVF=yes RVD=yes DEBUG_PLUGIN=RISCV WITH_RISCV_REF=no DEBUG_PLUGIN_EXTERNAL=yes DEBUG_PLUGIN=no VEXRISCV_JTAG=yes
*
@ -122,9 +122,7 @@ object GenFullWithOfficialRiscvDebug extends App{
)
)
def cpu() = new VexRiscv(config){
println(config.getRegressionArgs().mkString(" "))
}
def cpu() = new VexRiscv(config)
SpinalVerilog(cpu())
}