VexRiscvSmpCluster can now set regfile read kind
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0f1ca72171
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@ -15,7 +15,7 @@ import spinal.lib.generator.Handle
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import spinal.lib.misc.plic.PlicMapping
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import spinal.lib.system.debugger.SystemDebuggerConfig
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import vexriscv.ip.{DataCacheAck, DataCacheConfig, DataCacheMemBus, InstructionCache, InstructionCacheConfig}
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import vexriscv.plugin.{BranchPlugin, CsrAccess, CsrPlugin, CsrPluginConfig, DBusCachedPlugin, DBusSimplePlugin, DYNAMIC_TARGET, DebugPlugin, DecoderSimplePlugin, FullBarrelShifterPlugin, HazardSimplePlugin, IBusCachedPlugin, IBusSimplePlugin, IntAluPlugin, MmuPlugin, MmuPortConfig, MulDivIterativePlugin, MulPlugin, RegFilePlugin, STATIC, SrcPlugin, StaticMemoryTranslatorPlugin, YamlPlugin}
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import vexriscv.plugin.{BranchPlugin, CsrAccess, CsrPlugin, CsrPluginConfig, DBusCachedPlugin, DBusSimplePlugin, DYNAMIC_TARGET, DebugPlugin, DecoderSimplePlugin, FullBarrelShifterPlugin, HazardSimplePlugin, IBusCachedPlugin, IBusSimplePlugin, IntAluPlugin, MmuPlugin, MmuPortConfig, MulDivIterativePlugin, MulPlugin, RegFilePlugin, RegFileReadKind, STATIC, SrcPlugin, StaticMemoryTranslatorPlugin, YamlPlugin}
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import vexriscv.{Riscv, VexRiscv, VexRiscvBmbGenerator, VexRiscvConfig, plugin}
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import scala.collection.mutable
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@ -162,7 +162,8 @@ object VexRiscvSmpClusterGen {
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earlyBranch : Boolean = false,
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dBusCmdMasterPipe : Boolean = false,
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withMmu : Boolean = true,
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withSupervisor : Boolean = true
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withSupervisor : Boolean = true,
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regfileRead : RegFileReadKind = plugin.ASYNC
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) = {
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assert(iCacheSize/iCacheWays <= 4096, "Instruction cache ways can't be bigger than 4096 bytes")
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assert(dCacheSize/dCacheWays <= 4096, "Data cache ways can't be bigger than 4096 bytes")
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@ -236,7 +237,7 @@ object VexRiscvSmpClusterGen {
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catchIllegalInstruction = true
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),
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new RegFilePlugin(
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regFileReadyKind = plugin.ASYNC,
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regFileReadyKind = regfileRead,
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zeroBoot = false,
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x0Init = true
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),
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