Add tightly coupled interface to the i$
This commit is contained in:
Dolu1990
parent
8f1b4cc8e5
commit
f4598fbd0a
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@ -30,6 +30,13 @@ trait Pipeline {
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filtered.length != 0
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}
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def serviceElse[T](clazz : Class[T], default : => T) : T = {
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if(!serviceExist(clazz)) return default
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val filtered = plugins.filter(o => clazz.isAssignableFrom(o.getClass))
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assert(filtered.length == 1)
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filtered.head.asInstanceOf[T]
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}
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def update[T](that : PipelineConfig[T], value : T) : Unit = configs(that) = value
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def apply[T](that : PipelineConfig[T]) : T = configs(that).asInstanceOf[T]
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@ -39,6 +39,10 @@ trait PrivilegeService{
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def isUser(stage : Stage) : Bool
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}
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case class PrivilegeServiceDefault() extends PrivilegeService{
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override def isUser(stage: Stage): Bool = False
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}
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trait InterruptionInhibitor{
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def inhibateInterrupts() : Unit
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}
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@ -28,20 +28,20 @@ import spinal.lib.eda.altera.{InterruptReceiverTag, ResetEmitterTag}
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object TestsWorkspace {
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def main(args: Array[String]) {
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SpinalConfig(mergeAsyncProcess = false, anonymSignalPrefix = "zz_").generateVerilog {
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val configFull = VexRiscvConfig(
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def configFull = {
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val config = VexRiscvConfig(
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plugins = List(
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// new IBusSimplePlugin(
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// resetVector = 0x80000000l,
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// cmdForkOnSecondStage = false,
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// cmdForkPersistence = false,
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// prediction = NONE,
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// historyRamSizeLog2 = 10,
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// catchAccessFault = false,
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// compressedGen = false,
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// busLatencyMin = 1,
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// injectorStage = true
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// ),
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// new IBusSimplePlugin(
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// resetVector = 0x80000000l,
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// cmdForkOnSecondStage = false,
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// cmdForkPersistence = false,
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// prediction = NONE,
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// historyRamSizeLog2 = 10,
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// catchAccessFault = false,
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// compressedGen = false,
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// busLatencyMin = 1,
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// injectorStage = true
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// ),
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new IBusCachedPlugin(
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resetVector = 0x80000000l,
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compressedGen = false,
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@ -65,11 +65,12 @@ object TestsWorkspace {
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portTlbSize = 4
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)
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),
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// new DBusSimplePlugin(
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// catchAddressMisaligned = true,
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// catchAccessFault = false,
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// earlyInjection = false
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// ),
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// ).newTightlyCoupledPort(TightlyCoupledPortParameter("iBusTc", a => a(30 downto 28) === 0x0 && a(5))),
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// new DBusSimplePlugin(
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// catchAddressMisaligned = true,
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// catchAccessFault = false,
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// earlyInjection = false
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// ),
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new DBusCachedPlugin(
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config = new DataCacheConfig(
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cacheSize = 4096,
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@ -84,21 +85,21 @@ object TestsWorkspace {
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catchMemoryTranslationMiss = true,
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atomicEntriesCount = 2
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),
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// memoryTranslatorPortConfig = null
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// memoryTranslatorPortConfig = null
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memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
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portTlbSize = 6
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)
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),
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// new StaticMemoryTranslatorPlugin(
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// ioRange = _(31 downto 28) === 0xF
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// ),
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// new StaticMemoryTranslatorPlugin(
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// ioRange = _(31 downto 28) === 0xF
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// ),
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new MemoryTranslatorPlugin(
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tlbSize = 32,
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virtualRange = _(31 downto 28) === 0xC,
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ioRange = _(31 downto 28) === 0xF
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),
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new DecoderSimplePlugin(
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catchIllegalInstruction = false
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catchIllegalInstruction = true
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),
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new RegFilePlugin(
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regFileReadyKind = plugin.ASYNC,
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@ -109,7 +110,7 @@ object TestsWorkspace {
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separatedAddSub = false
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),
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new FullBarrelShifterPlugin(earlyInjection = true),
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// new LightShifterPlugin,
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// new LightShifterPlugin,
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new HazardSimplePlugin(
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bypassExecute = true,
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bypassMemory = true,
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@ -119,8 +120,8 @@ object TestsWorkspace {
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pessimisticWriteRegFile = false,
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pessimisticAddressMatch = false
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),
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// new HazardSimplePlugin(false, true, false, true),
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// new HazardSimplePlugin(false, false, false, false),
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// new HazardSimplePlugin(false, true, false, true),
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// new HazardSimplePlugin(false, false, false, false),
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new MulPlugin,
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new MulDivIterativePlugin(
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genMul = false,
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@ -128,31 +129,31 @@ object TestsWorkspace {
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mulUnrollFactor = 32,
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divUnrollFactor = 1
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),
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// new DivPlugin,
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// new DivPlugin,
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new CsrPlugin(CsrPluginConfig.all(0x80000020l)),
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// new CsrPlugin(//CsrPluginConfig.all2(0x80000020l).copy(ebreakGen = true)/*
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// CsrPluginConfig(
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// catchIllegalAccess = false,
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// mvendorid = null,
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// marchid = null,
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// mimpid = null,
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// mhartid = null,
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// misaExtensionsInit = 0,
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// misaAccess = CsrAccess.READ_ONLY,
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// mtvecAccess = CsrAccess.WRITE_ONLY,
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// mtvecInit = 0x80000020l,
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// mepcAccess = CsrAccess.READ_WRITE,
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// mscratchGen = true,
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// mcauseAccess = CsrAccess.READ_ONLY,
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// mbadaddrAccess = CsrAccess.READ_ONLY,
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// mcycleAccess = CsrAccess.NONE,
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// minstretAccess = CsrAccess.NONE,
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// ecallGen = true,
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// ebreakGen = true,
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// wfiGenAsWait = false,
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// wfiGenAsNop = true,
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// ucycleAccess = CsrAccess.NONE
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// )),
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// new CsrPlugin(//CsrPluginConfig.all2(0x80000020l).copy(ebreakGen = true)/*
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// CsrPluginConfig(
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// catchIllegalAccess = false,
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// mvendorid = null,
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// marchid = null,
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// mimpid = null,
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// mhartid = null,
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// misaExtensionsInit = 0,
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// misaAccess = CsrAccess.READ_ONLY,
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// mtvecAccess = CsrAccess.WRITE_ONLY,
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// mtvecInit = 0x80000020l,
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// mepcAccess = CsrAccess.READ_WRITE,
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// mscratchGen = true,
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// mcauseAccess = CsrAccess.READ_ONLY,
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// mbadaddrAccess = CsrAccess.READ_ONLY,
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// mcycleAccess = CsrAccess.NONE,
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// minstretAccess = CsrAccess.NONE,
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// ecallGen = true,
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// ebreakGen = true,
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// wfiGenAsWait = false,
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// wfiGenAsNop = true,
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// ucycleAccess = CsrAccess.NONE
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// )),
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new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))),
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new BranchPlugin(
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earlyBranch = true,
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@ -162,8 +163,28 @@ object TestsWorkspace {
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new YamlPlugin("cpu0.yaml")
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)
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)
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config
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}
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// import spinal.core.sim._
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// SimConfig.withConfig(SpinalConfig(mergeAsyncProcess = false, anonymSignalPrefix = "zz_")).allOptimisation.compile(new VexRiscv(configFull)).doSimUntilVoid{ dut =>
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// dut.clockDomain.forkStimulus(10)
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// dut.clockDomain.forkSimSpeedPrinter(4)
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// var iBus : InstructionCacheMemBus = null
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//
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// dut.plugins.foreach{
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// case plugin: IBusCachedPlugin => iBus = plugin.iBus
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// case _ =>
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// }
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// dut.clockDomain.onSamplings{
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//// iBus.cmd.ready.randomize()
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// iBus.rsp.data #= 0x13
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// }
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// }
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SpinalConfig(mergeAsyncProcess = false, anonymSignalPrefix = "zz_").generateVerilog {
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val toplevel = new VexRiscv(configFull)
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// val toplevel = new VexRiscv(configLight)
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@ -86,15 +86,17 @@ trait InstructionCacheCommons{
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val pc : UInt
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val physicalAddress : UInt
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val data : Bits
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val cacheMiss, error, mmuMiss, illegalAccess,isUser : Bool
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val cacheMiss, error, mmuMiss, illegalAccess, isUser : Bool
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}
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case class InstructionCacheCpuFetch(p : InstructionCacheConfig) extends Bundle with IMasterSlave with InstructionCacheCommons {
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val isValid = Bool
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val isStuck = Bool
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val isRemoved = Bool
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val isValid = Bool()
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val isStuck = Bool()
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val isRemoved = Bool()
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val pc = UInt(p.addressWidth bits)
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val data = Bits(p.cpuDataWidth bits)
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val data = Bits(p.cpuDataWidth bits)
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val dataBypassValid = Bool()
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val dataBypass = Bits(p.cpuDataWidth bits)
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val mmuBus = MemoryTranslatorBus()
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val physicalAddress = UInt(p.addressWidth bits)
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val cacheMiss, error, mmuMiss, illegalAccess,isUser = ifGen(!p.twoCycleCache)(Bool)
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@ -102,7 +104,7 @@ case class InstructionCacheCpuFetch(p : InstructionCacheConfig) extends Bundle w
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override def asMaster(): Unit = {
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out(isValid, isStuck, isRemoved, pc)
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inWithNull(error,mmuMiss,illegalAccess,data, cacheMiss,physicalAddress)
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outWithNull(isUser)
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outWithNull(isUser, dataBypass, dataBypassValid)
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slaveWithNull(mmuBus)
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}
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}
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@ -381,21 +383,21 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{
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}
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val hit = if(!twoCycleRam) new Area{
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val hit = (!twoCycleRam) generate new Area{
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val hits = read.waysValues.map(way => way.tag.valid && way.tag.address === io.cpu.fetch.mmuBus.rsp.physicalAddress(tagRange))
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val valid = Cat(hits).orR
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val id = OHToUInt(hits)
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val error = read.waysValues.map(_.tag.error).read(id)
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val data = read.waysValues.map(_.data).read(id)
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val word = data.subdivideIn(cpuDataWidth bits).read(io.cpu.fetch.pc(memWordToCpuWordRange))
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io.cpu.fetch.data := word
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io.cpu.fetch.data := (io.cpu.fetch.dataBypassValid ? io.cpu.fetch.dataBypass | word)
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if(twoCycleCache){
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io.cpu.decode.data := RegNextWhen(io.cpu.fetch.data,!io.cpu.decode.isStuck)
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}
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} else null
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}
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if(twoCycleRam && wayCount == 1){
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io.cpu.fetch.data := read.waysValues.head.data.subdivideIn(cpuDataWidth bits).read(io.cpu.fetch.pc(memWordToCpuWordRange))
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io.cpu.fetch.data := (io.cpu.fetch.dataBypassValid ? io.cpu.fetch.dataBypass | read.waysValues.head.data.subdivideIn(cpuDataWidth bits).read(io.cpu.fetch.pc(memWordToCpuWordRange)))
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}
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io.cpu.fetch.mmuBus.cmd.isValid := io.cpu.fetch.isValid
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@ -405,7 +407,6 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{
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io.cpu.fetch.physicalAddress := io.cpu.fetch.mmuBus.rsp.physicalAddress
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val resolution = ifGen(!twoCycleCache)( new Area{
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// def stage[T <: Data](that : T) = RegNextWhen(that,!io.cpu.decode.isStuck)
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val mmuRsp = io.cpu.fetch.mmuBus.rsp
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io.cpu.fetch.cacheMiss := !hit.valid
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@ -432,17 +433,13 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{
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val error = tags(id).error
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val data = fetchStage.read.waysValues.map(way => stage(way.data)).read(id)
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val word = data.subdivideIn(cpuDataWidth bits).read(io.cpu.decode.pc(memWordToCpuWordRange))
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when(stage(io.cpu.fetch.dataBypassValid)){
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word := stage(io.cpu.fetch.dataBypass)
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}
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io.cpu.decode.data := word
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}
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io.cpu.decode.cacheMiss := !hit.valid
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// when( io.cpu.decode.isValid && io.cpu.decode.cacheMiss){
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// io.cpu.prefetch.haltIt := True
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// lineLoader.valid := True
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// lineLoader.address := mmuRsp.physicalAddress //Could be optimise if mmu not used
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// }
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// when(io.cpu)
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io.cpu.decode.error := hit.error
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io.cpu.decode.mmuMiss := mmuRsp.miss
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io.cpu.decode.illegalAccess := !mmuRsp.allowExecute || (io.cpu.decode.isUser && !mmuRsp.allowUser)
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@ -5,10 +5,26 @@ import vexriscv.ip._
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import spinal.core._
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import spinal.lib._
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import scala.collection.mutable.ArrayBuffer
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//class IBusCachedPlugin(config : InstructionCacheConfig, memoryTranslatorPortConfig : Any = null) extends Plugin[VexRiscv] {
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// var iBus : InstructionCacheMemBus = null
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// override def build(pipeline: VexRiscv): Unit = ???
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//}
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case class TightlyCoupledBus() extends Bundle with IMasterSlave {
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val enable = Bool()
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val address = UInt(32 bits)
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val data = Bits(32 bits)
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override def asMaster(): Unit = {
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out(enable, address)
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in(data)
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}
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}
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case class TightlyCoupledPortParameter(name : String, hit : UInt => Bool)
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case class TightlyCoupledPort(p : TightlyCoupledPortParameter, var bus : TightlyCoupledBus)
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class IBusCachedPlugin(resetVector : BigInt = 0x80000000l,
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relaxedPcCalculation : Boolean = false,
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prediction : BranchPrediction = NONE,
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@ -36,6 +52,15 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l,
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var privilegeService : PrivilegeService = null
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var redoBranch : Flow[UInt] = null
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var decodeExceptionPort : Flow[ExceptionCause] = null
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val tightlyCoupledPorts = ArrayBuffer[TightlyCoupledPort]()
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def newTightlyCoupledPort(p : TightlyCoupledPortParameter) = {
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val port = TightlyCoupledPort(p, null)
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tightlyCoupledPorts += port
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this
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}
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object FLUSH_ALL extends Stageable(Bool)
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object IBUS_ACCESS_ERROR extends Stageable(Bool)
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@ -66,8 +91,7 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l,
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if(pipeline.serviceExist(classOf[MemoryTranslator]))
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mmuBus = pipeline.service(classOf[MemoryTranslator]).newTranslationPort(MemoryTranslatorPort.PRIORITY_INSTRUCTION, memoryTranslatorPortConfig)
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if(pipeline.serviceExist(classOf[PrivilegeService]))
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privilegeService = pipeline.service(classOf[PrivilegeService])
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privilegeService = pipeline.serviceElse(classOf[PrivilegeService], PrivilegeServiceDefault())
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if(pipeline.serviceExist(classOf[ReportService])){
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val report = pipeline.service(classOf[ReportService])
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@ -98,21 +122,106 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l,
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val cache = new InstructionCache(IBusCachedPlugin.this.config)
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iBus = master(new InstructionCacheMemBus(IBusCachedPlugin.this.config)).setName("iBus")
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iBus <> cache.io.mem
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iBus.cmd.address.allowOverride := cache.io.mem.cmd.address // - debugAddressOffset
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iBus.cmd.address.allowOverride := cache.io.mem.cmd.address
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val stageOffset = if(relaxedPcCalculation) 1 else 0
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def stages = iBusRsp.stages.drop(stageOffset)
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//Connect prefetch cache side
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cache.io.cpu.prefetch.isValid := stages(0).input.valid
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cache.io.cpu.prefetch.pc := stages(0).input.payload
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stages(0).halt setWhen(cache.io.cpu.prefetch.haltIt)
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tightlyCoupledPorts.foreach(p => p.bus = master(TightlyCoupledBus()).setName(p.p.name))
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val s0 = new Area {
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//address decoding
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val tightlyCoupledHits = Vec(tightlyCoupledPorts.map(_.p.hit(stages(0).input.payload)))
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val tightlyCoupledHit = tightlyCoupledHits.orR
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for((port, hit) <- (tightlyCoupledPorts, tightlyCoupledHits).zipped){
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port.bus.enable := stages(0).input.fire && hit
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port.bus.address := stages(0).input.payload(31 downto 2) @@ U"00"
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}
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//Connect prefetch cache side
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cache.io.cpu.prefetch.isValid := stages(0).input.valid && !tightlyCoupledHit
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cache.io.cpu.prefetch.pc := stages(0).input.payload
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stages(0).halt setWhen (cache.io.cpu.prefetch.haltIt)
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cache.io.cpu.fetch.isRemoved := flush
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val iBusRspOutputHalt = False
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cache.io.cpu.fetch.isRemoved := flush
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}
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val s1 = new Area {
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val tightlyCoupledHits = RegNextWhen(s0.tightlyCoupledHits, stages(1).input.ready)
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val tightlyCoupledHit = RegNextWhen(s0.tightlyCoupledHit, stages(1).input.ready)
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cache.io.cpu.fetch.dataBypassValid := tightlyCoupledHit
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cache.io.cpu.fetch.dataBypass := (if(tightlyCoupledPorts.isEmpty) B(0) else MuxOH(tightlyCoupledHits, tightlyCoupledPorts.map(e => CombInit(e.bus.data))))
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//Connect fetch cache side
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cache.io.cpu.fetch.isValid := stages(1).input.valid && !tightlyCoupledHit
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cache.io.cpu.fetch.isStuck := !stages(1).input.ready
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cache.io.cpu.fetch.pc := stages(1).input.payload
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if (!twoCycleCache) {
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cache.io.cpu.fetch.isUser := privilegeService.isUser(decode)
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}
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}
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val s2 = twoCycleCache generate new Area {
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val tightlyCoupledHit = RegNextWhen(s1.tightlyCoupledHit, stages(2).input.ready)
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cache.io.cpu.decode.isValid := stages(2).input.valid && !tightlyCoupledHit
|
||||
cache.io.cpu.decode.isStuck := !stages(2).input.ready
|
||||
cache.io.cpu.decode.pc := stages(2).input.payload
|
||||
cache.io.cpu.decode.isUser := privilegeService.isUser(decode)
|
||||
|
||||
if ((!twoCycleRam || wayCount == 1) && !compressedGen && !injectorStage) {
|
||||
decode.insert(INSTRUCTION_ANTICIPATED) := Mux(decode.arbitration.isStuck, decode.input(INSTRUCTION), cache.io.cpu.fetch.data)
|
||||
}
|
||||
}
|
||||
|
||||
val rsp = new Area {
|
||||
val iBusRspOutputHalt = False
|
||||
|
||||
val cacheRsp = if (twoCycleCache) cache.io.cpu.decode else cache.io.cpu.fetch
|
||||
val cacheRspArbitration = stages(if (twoCycleCache) 2 else 1)
|
||||
var issueDetected = False
|
||||
val redoFetch = False //RegNext(False) init(False)
|
||||
when(cacheRsp.isValid && cacheRsp.cacheMiss && !issueDetected) {
|
||||
issueDetected \= True
|
||||
redoFetch := iBusRsp.readyForError
|
||||
}
|
||||
|
||||
|
||||
//Refill / redo
|
||||
assert(decodePcGen == compressedGen)
|
||||
cache.io.cpu.fill.valid := redoFetch
|
||||
cache.io.cpu.fill.payload := cacheRsp.physicalAddress
|
||||
redoBranch.valid := redoFetch
|
||||
redoBranch.payload := (if (decodePcGen) decode.input(PC) else cacheRsp.pc)
|
||||
|
||||
if (catchSomething) {
|
||||
val accessFault = if (catchAccessFault) cacheRsp.error else False
|
||||
val mmuMiss = if (catchMemoryTranslationMiss) cacheRsp.mmuMiss else False
|
||||
val illegalAccess = if (catchIllegalAccess) cacheRsp.illegalAccess else False
|
||||
|
||||
decodeExceptionPort.valid := False
|
||||
decodeExceptionPort.code := mmuMiss ? U(14) | 1
|
||||
decodeExceptionPort.badAddr := cacheRsp.pc
|
||||
when(cacheRsp.isValid && (accessFault || mmuMiss || illegalAccess) && !issueDetected) {
|
||||
issueDetected \= True
|
||||
decodeExceptionPort.valid := iBusRsp.readyForError
|
||||
}
|
||||
}
|
||||
|
||||
cacheRspArbitration.halt setWhen (issueDetected || iBusRspOutputHalt)
|
||||
iBusRsp.output.valid := cacheRspArbitration.output.valid
|
||||
cacheRspArbitration.output.ready := iBusRsp.output.ready
|
||||
iBusRsp.output.rsp.inst := cacheRsp.data
|
||||
iBusRsp.output.pc := cacheRspArbitration.output.payload
|
||||
}
|
||||
|
||||
if (mmuBus != null) {
|
||||
cache.io.cpu.fetch.mmuBus <> mmuBus
|
||||
(if(twoCycleCache) stages(1).halt else iBusRspOutputHalt) setWhen(mmuBus.cmd.isValid && !mmuBus.rsp.hit && !mmuBus.rsp.miss)
|
||||
(if (twoCycleCache) stages(1).halt else rsp.iBusRspOutputHalt) setWhen (mmuBus.cmd.isValid && !mmuBus.rsp.hit && !mmuBus.rsp.miss)
|
||||
} else {
|
||||
cache.io.cpu.fetch.mmuBus.rsp.physicalAddress := cache.io.cpu.fetch.mmuBus.cmd.virtualAddress
|
||||
cache.io.cpu.fetch.mmuBus.rsp.allowExecute := True
|
||||
|
|
@ -124,64 +233,6 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l,
|
|||
cache.io.cpu.fetch.mmuBus.rsp.hit := False
|
||||
}
|
||||
|
||||
//Connect fetch cache side
|
||||
cache.io.cpu.fetch.isValid := stages(1).input.valid
|
||||
cache.io.cpu.fetch.isStuck := !stages(1).input.ready
|
||||
cache.io.cpu.fetch.pc := stages(1).input.payload
|
||||
|
||||
|
||||
if(twoCycleCache){
|
||||
cache.io.cpu.decode.isValid := stages(2).input.valid
|
||||
cache.io.cpu.decode.isStuck := !stages(2).input.ready
|
||||
cache.io.cpu.decode.pc := stages(2).input.payload
|
||||
cache.io.cpu.decode.isUser := (if (privilegeService != null) privilegeService.isUser(decode) else False)
|
||||
|
||||
if((!twoCycleRam || wayCount == 1) && !compressedGen && !injectorStage){
|
||||
decode.insert(INSTRUCTION_ANTICIPATED) := Mux(decode.arbitration.isStuck, decode.input(INSTRUCTION), cache.io.cpu.fetch.data)
|
||||
}
|
||||
} else {
|
||||
cache.io.cpu.fetch.isUser := (if (privilegeService != null) privilegeService.isUser(decode) else False)
|
||||
}
|
||||
|
||||
|
||||
|
||||
// val missHalt = cache.io.cpu.fetch.isValid && cache.io.cpu.fetch.cacheMiss
|
||||
val cacheRsp = if(twoCycleCache) cache.io.cpu.decode else cache.io.cpu.fetch
|
||||
val cacheRspArbitration = stages(if(twoCycleCache) 2 else 1)
|
||||
var issueDetected = False
|
||||
val redoFetch = False //RegNext(False) init(False)
|
||||
when(cacheRsp.isValid && cacheRsp.cacheMiss && !issueDetected){
|
||||
issueDetected \= True
|
||||
redoFetch := iBusRsp.readyForError
|
||||
}
|
||||
|
||||
|
||||
assert(decodePcGen == compressedGen)
|
||||
cache.io.cpu.fill.valid := redoFetch
|
||||
redoBranch.valid := redoFetch
|
||||
redoBranch.payload := (if(decodePcGen) decode.input(PC) else cacheRsp.pc)
|
||||
cache.io.cpu.fill.payload := cacheRsp.physicalAddress
|
||||
|
||||
if(catchSomething){
|
||||
val accessFault = if (catchAccessFault) cacheRsp.error else False
|
||||
val mmuMiss = if (catchMemoryTranslationMiss) cacheRsp.mmuMiss else False
|
||||
val illegalAccess = if (catchIllegalAccess) cacheRsp.illegalAccess else False
|
||||
|
||||
decodeExceptionPort.valid := False
|
||||
decodeExceptionPort.code := mmuMiss ? U(14) | 1
|
||||
decodeExceptionPort.badAddr := cacheRsp.pc
|
||||
when(cacheRsp.isValid && (accessFault || mmuMiss || illegalAccess) && !issueDetected){
|
||||
issueDetected \= True
|
||||
decodeExceptionPort.valid := iBusRsp.readyForError
|
||||
}
|
||||
}
|
||||
|
||||
cacheRspArbitration.halt setWhen(issueDetected || iBusRspOutputHalt)
|
||||
iBusRsp.output.arbitrationFrom(cacheRspArbitration.output)
|
||||
iBusRsp.output.rsp.inst := cacheRsp.data
|
||||
iBusRsp.output.pc := cacheRspArbitration.output.payload
|
||||
|
||||
|
||||
val flushStage = if(memory != null) memory else execute
|
||||
flushStage plug new Area {
|
||||
import flushStage._
|
||||
|
|
|
|||
|
|
@ -1192,6 +1192,43 @@ public:
|
|||
};
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef IBUS_TC
|
||||
|
||||
class IBusTc : public SimElement{
|
||||
public:
|
||||
|
||||
uint32_t nextData;
|
||||
|
||||
Workspace *ws;
|
||||
VVexRiscv* top;
|
||||
IBusTc(Workspace* ws){
|
||||
this->ws = ws;
|
||||
this->top = ws->top;
|
||||
}
|
||||
|
||||
virtual void onReset(){
|
||||
}
|
||||
|
||||
virtual void preCycle(){
|
||||
if (top->iBusTc_enable) {
|
||||
if((top->iBusTc_address & 0x70000000) != 0 || (top->iBusTc_address & 0x20) == 0){
|
||||
printf("IBusTc access out of range\n");
|
||||
ws->fail();
|
||||
}
|
||||
bool error_next;
|
||||
ws->iBusAccess(top->iBusTc_address, &nextData,&error_next);
|
||||
}
|
||||
}
|
||||
|
||||
virtual void postCycle(){
|
||||
top->iBusTc_data = nextData;
|
||||
}
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef IBUS_SIMPLE_AVALON
|
||||
|
||||
struct IBusSimpleAvalonRsp{
|
||||
|
|
@ -1274,6 +1311,12 @@ public:
|
|||
bool error;
|
||||
top->iBus_rsp_valid = 0;
|
||||
if(pendingCount != 0 && (!ws->iStall || VL_RANDOM_I(7) < 100)){
|
||||
#ifdef IBUS_TC
|
||||
if((address & 0x70000000) == 0 && (address & 0x20) != 0){
|
||||
printf("IBUS_CACHED access out of range\n");
|
||||
ws->fail();
|
||||
}
|
||||
#endif
|
||||
ws->iBusAccess(address,&top->iBus_rsp_payload_data,&error);
|
||||
top->iBus_rsp_payload_error = error;
|
||||
pendingCount--;
|
||||
|
|
@ -1960,6 +2003,11 @@ void Workspace::fillSimELements(){
|
|||
#if defined(IBUS_CACHED_WISHBONE) || defined(IBUS_SIMPLE_WISHBONE)
|
||||
simElements.push_back(new IBusCachedWishbone(this));
|
||||
#endif
|
||||
|
||||
#ifdef IBUS_TC
|
||||
simElements.push_back(new IBusTc(this));
|
||||
#endif
|
||||
|
||||
#ifdef DBUS_SIMPLE
|
||||
simElements.push_back(new DBusSimple(this));
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
DEBUG?=no
|
||||
|
||||
IBUS?=CACHED
|
||||
IBUS_TC?=no
|
||||
DBUS?=CACHED
|
||||
TRACE?=no
|
||||
TRACE_ACCESS?=no
|
||||
|
|
@ -42,7 +43,7 @@ ADDCFLAGS += -CFLAGS -DTHREAD_COUNT=${THREAD_COUNT}
|
|||
ifeq ($(DEBUG),yes)
|
||||
ADDCFLAGS += -CFLAGS -O0 -CFLAGS -g
|
||||
else
|
||||
ADDCFLAGS += -CFLAGS -O3
|
||||
ADDCFLAGS += -CFLAGS -O3 -O3
|
||||
endif
|
||||
|
||||
|
||||
|
|
@ -58,6 +59,11 @@ ifneq ($(RUN_HEX),no)
|
|||
ADDCFLAGS += -CFLAGS -DRUN_HEX='\"$(RUN_HEX)\"'
|
||||
endif
|
||||
|
||||
|
||||
ifeq ($(IBUS_TC),yes)
|
||||
ADDCFLAGS += -CFLAGS -DIBUS_TC=yes
|
||||
endif
|
||||
|
||||
ifeq ($(COMPRESSED),yes)
|
||||
ADDCFLAGS += -CFLAGS -DCOMPRESSED
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -284,6 +284,8 @@ class IBusDimension extends VexRiscvDimension("IBus") {
|
|||
}
|
||||
} else {
|
||||
val compressed = r.nextBoolean()
|
||||
val tighlyCoupled = r.nextBoolean()
|
||||
// val tighlyCoupled = false
|
||||
val prediction = random(r, List(NONE, STATIC, DYNAMIC, DYNAMIC_TARGET))
|
||||
val catchAll = universes.contains(VexRiscvUniverse.CATCH_ALL)
|
||||
val relaxedPcCalculation, twoCycleCache, injectorStage = r.nextBoolean()
|
||||
|
|
@ -295,29 +297,33 @@ class IBusDimension extends VexRiscvDimension("IBus") {
|
|||
wayCount = 1 << r.nextInt(3)
|
||||
}while(cacheSize/wayCount < 512)
|
||||
|
||||
new VexRiscvPosition("Cached" + (if(twoCycleCache) "2cc" else "") + (if(injectorStage) "Injstage" else "") + (if(twoCycleRam) "2cr" else "") + "S" + cacheSize + "W" + wayCount + (if(relaxedPcCalculation) "Relax" else "") + (if(compressed) "Rvc" else "") + prediction.getClass.getTypeName().replace("$","")) with InstructionAnticipatedPosition{
|
||||
override def testParam = "IBUS=CACHED" + (if(compressed) " COMPRESSED=yes" else "")
|
||||
override def applyOn(config: VexRiscvConfig): Unit = config.plugins += new IBusCachedPlugin(
|
||||
resetVector = 0x80000000l,
|
||||
compressedGen = compressed,
|
||||
prediction = prediction,
|
||||
relaxedPcCalculation = relaxedPcCalculation,
|
||||
injectorStage = injectorStage,
|
||||
config = InstructionCacheConfig(
|
||||
cacheSize = cacheSize,
|
||||
bytePerLine = 32,
|
||||
wayCount = wayCount,
|
||||
addressWidth = 32,
|
||||
cpuDataWidth = 32,
|
||||
memDataWidth = 32,
|
||||
catchIllegalAccess = catchAll,
|
||||
catchAccessFault = catchAll,
|
||||
catchMemoryTranslationMiss = catchAll,
|
||||
asyncTagMemory = false,
|
||||
twoCycleRam = twoCycleRam,
|
||||
twoCycleCache = twoCycleCache
|
||||
new VexRiscvPosition("Cached" + (if(twoCycleCache) "2cc" else "") + (if(injectorStage) "Injstage" else "") + (if(twoCycleRam) "2cr" else "") + "S" + cacheSize + "W" + wayCount + (if(relaxedPcCalculation) "Relax" else "") + (if(compressed) "Rvc" else "") + prediction.getClass.getTypeName().replace("$","")+ (if(tighlyCoupled)"Tc" else "")) with InstructionAnticipatedPosition{
|
||||
override def testParam = "IBUS=CACHED" + (if(compressed) " COMPRESSED=yes" else "") + (if(tighlyCoupled)" IBUS_TC=yes" else "")
|
||||
override def applyOn(config: VexRiscvConfig): Unit = {
|
||||
val p = new IBusCachedPlugin(
|
||||
resetVector = 0x80000000l,
|
||||
compressedGen = compressed,
|
||||
prediction = prediction,
|
||||
relaxedPcCalculation = relaxedPcCalculation,
|
||||
injectorStage = injectorStage,
|
||||
config = InstructionCacheConfig(
|
||||
cacheSize = cacheSize,
|
||||
bytePerLine = 32,
|
||||
wayCount = wayCount,
|
||||
addressWidth = 32,
|
||||
cpuDataWidth = 32,
|
||||
memDataWidth = 32,
|
||||
catchIllegalAccess = catchAll,
|
||||
catchAccessFault = catchAll,
|
||||
catchMemoryTranslationMiss = catchAll,
|
||||
asyncTagMemory = false,
|
||||
twoCycleRam = twoCycleRam,
|
||||
twoCycleCache = twoCycleCache
|
||||
)
|
||||
)
|
||||
)
|
||||
if(tighlyCoupled) p.newTightlyCoupledPort(TightlyCoupledPortParameter("iBusTc", a => a(30 downto 28) === 0x0 && a(5)))
|
||||
config.plugins += p
|
||||
}
|
||||
override def instructionAnticipatedOk() = !twoCycleCache || ((!twoCycleRam || wayCount == 1) && !compressed)
|
||||
}
|
||||
}
|
||||
|
|
@ -523,8 +529,8 @@ class TestIndividualFeatures extends FunSuite {
|
|||
|
||||
|
||||
// val testId = Some(mutable.HashSet[Int](0,28,45,93))
|
||||
// val testId = Some(mutable.HashSet[Int](5))
|
||||
// val seed = -2089952013329208578l
|
||||
// val testId = Some(mutable.HashSet[Int](31))
|
||||
// val seed = -7716775349351274630l
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue