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VexRiscv
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Fix info to flush data cache 

Briey sim add VGA GUI (SDL2)
Add DE0-Nano Briey support
This commit is contained in:
Charles Papon 2017-07-09 01:00:46 +02:00
parent 8d34c04425
commit f51f28164a
6 changed files with 221 additions and 107 deletions
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8
README.md
View File

@ -103,6 +103,14 @@ continue
## Using eclipse to run the software and debug it
You can use the eclipse + zilin embedded CDT plugin to do it.
## Briey SoC
WIP
```
sudo apt-get install libsdl2-dev
sudo apt-get install build-essential xorg-dev libudev-dev libts-dev libgl1-mesa-dev libglu1-mesa-dev libasound2-dev libpulse-dev libopenal-dev libogg-dev libvorbis-dev libaudiofile-dev libpng12-dev libfreetype6-dev libusb-dev libdbus-1-dev zlib1g-dev libdirectfb-dev
```
## Cpu plugin structure
There is an example of an pseudo ALU plugin :

2
src/main/scala/VexRiscv/Plugin/DBusCachedPlugin.scala
View File

@ -71,8 +71,8 @@ class DBusCachedPlugin(config : DataCacheConfig, memoryTranslatorPortConfig : An
e.kind = "cached"
e.flushInstructions.add(0x13 | (1 << 7)) ////ADDI x1, x0, 0
for(idx <- 0 until cacheSize by bytePerLine){
e.flushInstructions.add(0x13 + (1 << 7) + (1 << 15) + (bytePerLine << 20)) //ADDI x1, x1, 32
e.flushInstructions.add(0x7000500F + (1 << 15)) //Clean invalid data cache way x1
e.flushInstructions.add(0x13 + (1 << 7) + (1 << 15) + (bytePerLine << 20)) //ADDI x1, x1, 32
}
e.info = c

35
src/main/scala/VexRiscv/demo/Briey.scala
View File

@ -385,7 +385,7 @@ class Briey(config: BrieyConfig) extends Component{
io.vga <> axi.vgaCtrl.io.vga
}
//DE1-SoC
object Briey{
def main(args: Array[String]) {
val config = SpinalConfig()
@ -394,4 +394,37 @@ object Briey{
toplevel
})
}
}
//DE0-Nano
object BrieyDe0Nano{
def main(args: Array[String]) {
object IS42x160G {
def layout = SdramLayout(
bankWidth = 2,
columnWidth = 9,
rowWidth = 13,
dataWidth = 16
)
def timingGrade7 = SdramTimings(
bootRefreshCount = 8,
tPOW = 100 us,
tREF = 64 ms,
tRC = 60 ns,
tRFC = 60 ns,
tRAS = 37 ns,
tRP = 15 ns,
tRCD = 15 ns,
cMRD = 2,
tWR = 10 ns,
cWR = 1
)
}
val config = SpinalConfig()
config.generateVerilog({
val toplevel = new Briey(BrieyConfig.default.copy(sdramLayout = IS42x160G.layout))
toplevel
})
}
}

151
src/test/cpp/briey/main.cpp
View File

@ -759,6 +759,126 @@ public:
}
};
#include <SDL2/SDL.h>
#include <assert.h>
#include <stdint.h>
#include <stdlib.h>
class Display : public SimElement{
public:
int width, height;
uint32_t *pixels;
SDL_Window* window;
SDL_Renderer* renderer;
SDL_Texture * texture;
uint32_t x,y;
uint32_t refreshCounter = 0;
Display(int width, int height){
this->width = width;
this->height = height;
x = y = 0;
init();
}
virtual ~Display(){
delete[] pixels;
SDL_DestroyTexture(texture);
SDL_DestroyRenderer(renderer);
SDL_DestroyWindow(window);
SDL_Quit();
}
void init(){
/* Initialize SDL. */
if (SDL_Init(SDL_INIT_VIDEO) < 0)
return;
/* Create the window where we will draw. */
window = SDL_CreateWindow("VGA",
SDL_WINDOWPOS_CENTERED, SDL_WINDOWPOS_CENTERED,
width, height,
SDL_WINDOW_SHOWN);
/* We must call SDL_CreateRenderer in order for draw calls to affect this window. */
renderer = SDL_CreateRenderer(window, -1, 0);
texture = SDL_CreateTexture(renderer,
SDL_PIXELFORMAT_ARGB8888, SDL_TEXTUREACCESS_STATIC, width, height);
pixels = new Uint32[width * height];
memset(pixels, 0, width * height * sizeof(Uint32));
}
void set(uint32_t color){
pixels[x + y*width] = color;
}
void incX(){
x++;
if(x >= width) x = width;
}
void incY(){
y++;
if(y >= height) y = height;
}
void refresh(){
cout << "Display refresh " << refreshCounter++ << endl;
SDL_UpdateTexture(texture, NULL, pixels, 640 * sizeof(Uint32));
SDL_RenderClear(renderer);
SDL_RenderCopy(renderer, texture, NULL, NULL);
SDL_RenderPresent(renderer);
}
virtual void postCycle(){
}
virtual void preCycle(){
}
};
class Vga : public Display{
public:
VBriey* top;
Vga(VBriey* top,int width, int height) : Display(width, height){
this->top = top;
}
virtual ~Vga(){
}
virtual void postCycle(){
}
uint32_t lastvSync = 0,lasthSync = 0;
virtual void preCycle(){
if(!top->io_vga_vSync && lastvSync) {
y = 0;
refresh();
}
if(!top->io_vga_hSync && lasthSync && x != 0) {
incY();
x = 0;
}
if(top->io_vga_colorEn){
this->set((top->io_vga_color_r << 19) + (top->io_vga_color_g << 10) + (top->io_vga_color_b << 3));
incX();
}
lastvSync = top->io_vga_vSync;
lasthSync = top->io_vga_hSync;
}
};
class BrieyWorkspace : public Workspace{
public:
BrieyWorkspace() : Workspace("Briey"){
@ -800,6 +920,11 @@ public:
#endif
axiClk->add(new VexRiscvTracer(top->Briey->axi_core_cpu));
#ifdef VGA
Vga *vga = new Vga(top,640,480);
vgaClk->add(vga);
#endif
}
@ -824,30 +949,10 @@ long timer_end(struct timespec start_time){
/*
#include <boost/coroutine2/all.hpp>
#include <functional>
#include <iostream>
using boost::coroutines2::coroutine;
void cooperative(coroutine<int>::push_type &sink, int i)
{
int j = i;
sink(++j);
sink(++j);
std::cout << "end\n";
}
int main2()
{
using std::placeholders::_1;
coroutine<int>::pull_type source{std::bind(cooperative, _1, 0)};
std::cout << source.get() << '\n';
source();
std::cout << source.get() << '\n';
source();
}*/
int main(int argc, char **argv, char **env) {
@ -862,10 +967,6 @@ int main(int argc, char **argv, char **env) {
uint64_t duration = timer_end(startedAt);
cout << endl << "****************************************************************" << endl;
cout << "Had simulate " << Workspace::cycles << " clock cycles in " << duration*1e-9 << " s (" << Workspace::cycles / (duration*1e-9) << " Khz)" << endl;
/*if(successCounter == testsCounter)
cout << "SUCCESS " << successCounter << "/" << testsCounter << endl;
else
cout<< "FAILURE " << testsCounter - successCounter << "/" << testsCounter << endl;*/
cout << "****************************************************************" << endl << endl;

8
src/test/cpp/briey/makefile
View File

@ -3,8 +3,13 @@ TRACE?=no
TRACE_INSTRUCTION?=no
TRACE_REG?=no
PRINT_PERF?=no
VGA?=yes
TRACE_START=0
ADDCFLAGS += -CFLAGS -pthread
ADDCFLAGS += -CFLAGS -lSDL2
ADDCFLAGS += -LDFLAGS -lSDL2
ifeq ($(TRACE),yes)
VERILATOR_ARGS += --trace
@ -20,6 +25,9 @@ ifeq ($(PRINT_PERF),yes)
ADDCFLAGS += -CFLAGS -DPRINT_PERF
endif
ifeq ($(VGA),yes)
ADDCFLAGS += -CFLAGS -DVGA
endif
ifeq ($(TRACE_INSTRUCTION),yes)
ADDCFLAGS += -CFLAGS -DTRACE_INSTRUCTION
endif

124
src/test/cpp/briey/wip.gtkw
View File

@ -1,102 +1,66 @@
[*]
[*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI
[*] Fri Jun 23 12:04:47 2017
[*] Sat Jul 8 21:52:29 2017
[*]
[dumpfile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/briey/fail/Briey.vcd"
[dumpfile_mtime] "Fri Jun 23 09:43:01 2017"
[dumpfile_size] 1976675834
[dumpfile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/briey/Briey.vcd"
[dumpfile_mtime] "Sat Jul 8 21:52:14 2017"
[dumpfile_size] 1407698718
[savefile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/briey/wip.gtkw"
[timestart] 174298398700
[timestart] 24655083000
[size] 1776 953
[pos] -1 -353
*-17.000000 174298828600 174053720000 174335369100 174375180000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[pos] -1 -1
*-18.000000 24656341000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] TOP.
[treeopen] TOP.Briey.
[treeopen] TOP.Briey.axi_core_cpu.
[treeopen] TOP.Briey.axi_sdramCtrl.
[sst_width] 269
[signals_width] 586
[treeopen] TOP.Briey.axi_vgaCtrl.
[sst_width] 201
[signals_width] 356
[sst_expanded] 1
[sst_vpaned_height] 503
[sst_vpaned_height] 279
@23
TOP.Briey.axi_vgaCtrl.io_apb_PADDR[7:0]
@28
TOP.Briey.axi_core_cpu.DebugPlugin_haltIt
TOP.Briey.axi_core_cpu.DebugPlugin_haltedByBreak
TOP.Briey.axi_vgaCtrl.io_apb_PENABLE
@22
TOP.Briey.axi_core_cpu.writeBack_PC[31:0]
TOP.Briey.axi_vgaCtrl.io_apb_PRDATA[31:0]
@28
TOP.Briey.axi_core_cpu.writeBack_arbitration_isFiring
TOP.Briey.axi_vgaCtrl.io_apb_PREADY
TOP.Briey.axi_vgaCtrl.io_apb_PSEL[0]
@22
TOP.Briey.axi_core_cpu.writeBack_PC[31:0]
TOP.Briey.axi_core_cpu.RegFilePlugin_regFile(12)[31:0]
TOP.Briey.axi_core_cpu.RegFilePlugin_regFile(13)[31:0]
TOP.Briey.axi_core_cpu.RegFilePlugin_regFile(15)[31:0]
@800022
#{TOP.Briey.axi_core_cpu.writeBack_RegFilePlugin_regFileWrite_payload_address[0:4]} (4)TOP.Briey.axi_core_cpu.writeBack_RegFilePlugin_regFileWrite_payload_address[4:0] (3)TOP.Briey.axi_core_cpu.writeBack_RegFilePlugin_regFileWrite_payload_address[4:0] (2)TOP.Briey.axi_core_cpu.writeBack_RegFilePlugin_regFileWrite_payload_address[4:0] (1)TOP.Briey.axi_core_cpu.writeBack_RegFilePlugin_regFileWrite_payload_address[4:0] (0)TOP.Briey.axi_core_cpu.writeBack_RegFilePlugin_regFileWrite_payload_address[4:0]
@24
TOP.Briey.axi_core_cpu.writeBack_RegFilePlugin_regFileWrite_payload_address[4:0]
@1001200
-group_end
@22
TOP.Briey.axi_core_cpu.writeBack_RegFilePlugin_regFileWrite_payload_data[31:0]
TOP.Briey.axi_vgaCtrl.io_apb_PWDATA[31:0]
@28
TOP.Briey.axi_core_cpu.writeBack_RegFilePlugin_regFileWrite_valid
TOP.Briey.axi_vgaCtrl.io_apb_PWRITE
TOP.Briey.axi_vgaCtrl.io_axiClk
@22
TOP.Briey.axi_core_cpu.RegFilePlugin_regFile(2)[31:0]
TOP.Briey.axi_core_cpu.dataCache_1.io_cpu_writeBack_badAddr[31:0]
TOP.Briey.axi_vgaCtrl.io_axi_ar_payload_addr[31:0]
TOP.Briey.axi_vgaCtrl.io_axi_ar_payload_len[7:0]
@28
TOP.Briey.axi_core_cpu.dataCache_1.io_cpu_writeBack_haltIt
TOP.Briey.axi_core_cpu.dataCache_1.io_cpu_writeBack_isValid
TOP.Briey.axi_vgaCtrl.io_axi_ar_payload_size[2:0]
TOP.Briey.axi_vgaCtrl.io_axi_ar_ready
TOP.Briey.axi_vgaCtrl.io_axi_ar_valid
@22
TOP.Briey.axi_core_cpu.dBus_cmd_payload_address[31:0]
TOP.Briey.axi_core_cpu.dBus_cmd_payload_data[31:0]
TOP.Briey.axi_vgaCtrl.io_axi_r_payload_data[31:0]
@28
TOP.Briey.axi_core_cpu.dBus_cmd_payload_last
TOP.Briey.axi_core_cpu.dBus_cmd_payload_length[2:0]
TOP.Briey.axi_vgaCtrl.io_axi_r_payload_last
TOP.Briey.axi_vgaCtrl.io_axi_r_ready
TOP.Briey.axi_vgaCtrl.io_axi_r_valid
TOP.Briey.axi_vgaCtrl.io_vgaClk
TOP.Briey.axi_vgaCtrl.io_vga_colorEn
@22
TOP.Briey.axi_core_cpu.dBus_cmd_payload_mask[3:0]
TOP.Briey.axi_vgaCtrl.io_vga_color_b[4:0]
TOP.Briey.axi_vgaCtrl.io_vga_color_g[5:0]
TOP.Briey.axi_vgaCtrl.io_vga_color_r[4:0]
@28
TOP.Briey.axi_core_cpu.dBus_cmd_payload_wr
TOP.Briey.axi_core_cpu.dBus_cmd_ready
TOP.Briey.axi_core_cpu.dBus_cmd_valid
TOP.Briey.axi_vgaCtrl.io_vga_hSync
TOP.Briey.axi_vgaCtrl.io_vga_vSync
@22
TOP.Briey.axi_core_cpu.dBus_rsp_payload_data[31:0]
@28
TOP.Briey.axi_core_cpu.dBus_rsp_payload_error
TOP.Briey.axi_core_cpu.dBus_rsp_valid
@22
TOP.Briey.axi_ram.io_axi_r_payload_data[31:0]
TOP.Briey.axi_ram.io_axi_r_payload_id[3:0]
@28
TOP.Briey.axi_ram.io_axi_r_payload_last
TOP.Briey.axi_ram.io_axi_r_payload_resp[1:0]
TOP.Briey.axi_ram.io_axi_r_ready
TOP.Briey.axi_ram.io_axi_r_valid
@22
TOP.Briey.axi_core_cpu.dataCache_1.io_cpu_execute_args_address[31:0]
TOP.Briey.axi_core_cpu.dataCache_1.io_cpu_execute_args_data[31:0]
@28
TOP.Briey.axi_core_cpu.dataCache_1.io_cpu_execute_args_wr
TOP.Briey.axi_core_cpu.dataCache_1.io_cpu_execute_isValid
TOP.Briey.axi_core_cpu.execute_arbitration_isFiring
@22
TOP.Briey.axi_core_cpu.execute_PC[31:0]
TOP.Briey.axi_ram.io_axi_arw_payload_addr[11:0]
TOP.Briey.axi_ram.io_axi_arw_payload_len[7:0]
@28
TOP.Briey.axi_ram.io_axi_arw_payload_size[2:0]
TOP.Briey.axi_ram.io_axi_arw_payload_write
TOP.Briey.axi_ram.io_axi_arw_ready
TOP.Briey.axi_ram.io_axi_arw_valid
@22
TOP.Briey.axi_ram.io_axi_w_payload_data[31:0]
TOP.Briey.axi_ram.io_axi_w_payload_strb[3:0]
@28
TOP.Briey.axi_ram.io_axi_w_ready
TOP.Briey.axi_ram.io_axi_w_valid
TOP.Briey.axi_core_cpu.DebugPlugin_haltIt
@22
TOP.Briey.axi_core_cpu.execute_INSTRUCTION[31:0]
TOP.Briey.axi_core_cpu.RegFilePlugin_regFile(11)[31:0]
TOP.Briey.axi_core_cpu.RegFilePlugin_regFile(14)[31:0]
TOP.Briey.axi_vgaCtrl.vga_ctrl.io_timings_h_colorEnd[11:0]
TOP.Briey.axi_vgaCtrl.vga_ctrl.io_timings_h_colorStart[11:0]
TOP.Briey.axi_vgaCtrl.vga_ctrl.io_timings_h_syncEnd[11:0]
TOP.Briey.axi_vgaCtrl.vga_ctrl.io_timings_h_syncStart[11:0]
TOP.Briey.axi_vgaCtrl.vga_ctrl.io_timings_v_colorEnd[11:0]
TOP.Briey.axi_vgaCtrl.vga_ctrl.io_timings_v_colorStart[11:0]
TOP.Briey.axi_vgaCtrl.vga_ctrl.io_timings_v_syncEnd[11:0]
TOP.Briey.axi_vgaCtrl.vga_ctrl.io_timings_v_syncStart[11:0]
[pattern_trace] 1
[pattern_trace] 0