Fix CsrPlugin pipeline liberator
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@ -808,17 +808,29 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
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//Used to make the pipeline empty softly (for interrupts)
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//Used to make the pipeline empty softly (for interrupts)
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val pipelineLiberator = new Area{
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val pipelineLiberator = new Area{
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when(interrupt.valid && allowInterrupts){
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val pcValids = Vec(RegInit(False), stagesFromExecute.length)
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decode.arbitration.haltByOther := decode.arbitration.isValid
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val active = interrupt.valid && allowInterrupts && decode.arbitration.isValid
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when(active){
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decode.arbitration.haltByOther := True
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for((stage, reg, previous) <- (stagesFromExecute, pcValids, True :: pcValids.toList).zipped){
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when(!stage.arbitration.isStuck){
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reg := previous
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}
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}
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}
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when(!active || decode.arbitration.isRemoved) {
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pcValids.foreach(_ := False)
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}
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}
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val done = !stagesFromExecute.map(_.arbitration.isValid).orR && fetcher.pcValid(mepcCaptureStage)
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// val pcValids = for(stage <- stagesFromExecute) yield RegInit(False) clearWhen(!started) setWhen(!stage.arbitration.isValid)
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val done = CombInit(pcValids.last)
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if(exceptionPortCtrl != null) done.clearWhen(exceptionPortCtrl.exceptionValidsRegs.tail.orR)
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if(exceptionPortCtrl != null) done.clearWhen(exceptionPortCtrl.exceptionValidsRegs.tail.orR)
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}
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}
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//Interrupt/Exception entry logic
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//Interrupt/Exception entry logic
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val interruptJump = Bool.addTag(Verilator.public)
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val interruptJump = Bool.addTag(Verilator.public)
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interruptJump := interrupt.valid && pipelineLiberator.done && allowInterrupts
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interruptJump := interrupt.valid && pipelineLiberator.done && allowInterrupts
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if(pipelinedInterrupt) interrupt.valid clearWhen(interruptJump) //avoid double fireing
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val hadException = RegNext(exception) init(False)
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val hadException = RegNext(exception) init(False)
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pipelineLiberator.done.clearWhen(hadException)
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pipelineLiberator.done.clearWhen(hadException)
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