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VexRiscv
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Fix CsrPlugin pipeline liberator

This commit is contained in:
Charles Papon 2020-02-18 00:59:39 +01:00
parent 53a29e35e9
commit f63c4db469
1 changed files with 15 additions and 3 deletions
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18
src/main/scala/vexriscv/plugin/CsrPlugin.scala
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@ -808,17 +808,29 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
//Used to make the pipeline empty softly (for interrupts)
val pipelineLiberator = new Area{
when(interrupt.valid && allowInterrupts){
decode.arbitration.haltByOther := decode.arbitration.isValid
val pcValids = Vec(RegInit(False), stagesFromExecute.length)
val active = interrupt.valid && allowInterrupts && decode.arbitration.isValid
when(active){
decode.arbitration.haltByOther := True
for((stage, reg, previous) <- (stagesFromExecute, pcValids, True :: pcValids.toList).zipped){
when(!stage.arbitration.isStuck){
reg := previous
}
}
}
when(!active || decode.arbitration.isRemoved) {
pcValids.foreach(_ := False)
}
val done = !stagesFromExecute.map(_.arbitration.isValid).orR && fetcher.pcValid(mepcCaptureStage)
// val pcValids = for(stage <- stagesFromExecute) yield RegInit(False) clearWhen(!started) setWhen(!stage.arbitration.isValid)
val done = CombInit(pcValids.last)
if(exceptionPortCtrl != null) done.clearWhen(exceptionPortCtrl.exceptionValidsRegs.tail.orR)
}
//Interrupt/Exception entry logic
val interruptJump = Bool.addTag(Verilator.public)
interruptJump := interrupt.valid && pipelineLiberator.done && allowInterrupts
if(pipelinedInterrupt) interrupt.valid clearWhen(interruptJump) //avoid double fireing
val hadException = RegNext(exception) init(False)
pipelineLiberator.done.clearWhen(hadException)