mirror of
https://github.com/SpinalHDL/VexRiscv.git
synced 2025-01-03 03:43:39 -05:00
fpu got proper subnormal support, pass add/mul
This commit is contained in:
Dolu1990
parent
bdb5bc1180
commit
f818fb3ba4
4 changed files with 304 additions and 125 deletions
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@ -227,13 +227,13 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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val input = read.output.combStage()
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input.ready := False
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val loadHit = input.opcode === p.Opcode.LOAD
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val loadHit = List(FpuOpcode.LOAD, FpuOpcode.FMV_W_X).map(input.opcode === _).orR
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val load = Stream(LoadInput())
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load.valid := input.valid && loadHit
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input.ready setWhen(loadHit && load.ready)
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load.payload.assignSomeByName(read.output.payload)
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val shortPipHit = List(FpuOpcode.STORE, FpuOpcode.F2I, FpuOpcode.CMP, FpuOpcode.I2F, FpuOpcode.MIN_MAX, FpuOpcode.SGNJ, FpuOpcode.FMV_X_W, FpuOpcode.FMV_W_X, FpuOpcode.FCLASS).map(input.opcode === _).orR
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val shortPipHit = List(FpuOpcode.STORE, FpuOpcode.F2I, FpuOpcode.CMP, FpuOpcode.I2F, FpuOpcode.MIN_MAX, FpuOpcode.SGNJ, FpuOpcode.FMV_X_W, FpuOpcode.FCLASS).map(input.opcode === _).orR
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val shortPip = Stream(ShortPipInput())
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input.ready setWhen(shortPipHit && shortPip.ready)
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shortPip.valid := input.valid && shortPipHit
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@ -283,18 +283,43 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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}
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val load = new Area{
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case class S0() extends Bundle{
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val source = Source()
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val lockId = lockIdType()
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val rd = p.rfAddress()
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val value = FpuFloat(exponentSize = p.internalExponentSize-1, mantissaSize = p.internalMantissaSize)
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}
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val s0 = new Area{
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val input = decode.load.stage()
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val filtred = commitFork.load.map(port => port.takeWhen(port.load))
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val filtred = commitFork.load.map(port => port.takeWhen(port.sync))
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def feed = filtred(input.source)
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val hazard = !feed.valid
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val f32Mantissa = feed.value(0, 23 bits).asUInt
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val f32Exponent = feed.value(23, 8 bits).asUInt
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val f32Sign = feed.value(31)
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val output = input.haltWhen(hazard).swapPayload(S0())
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filtred.foreach(_.ready := False)
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feed.ready := input.valid && output.ready
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output.source := input.source
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output.lockId := input.lockId
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output.rd := input.rd
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output.value.mantissa := feed.value(0, 23 bits).asUInt
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output.value.exponent := feed.value(23, 8 bits).asUInt
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output.value.sign := feed.value(31)
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}
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val s1 = new Area{
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val input = s0.output.stage()
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val busy = False
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val f32Mantissa = input.value.mantissa
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val f32Exponent = input.value.exponent
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val f32Sign = input.value.sign
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val expZero = f32Exponent === 0
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val expOne = f32Exponent === 255
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val manZero = f32Mantissa === 0
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val manZeroReject = Reg(Bool()) setWhen(busy) clearWhen(!input.isStall)
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val manZero = f32Mantissa === 0 && !manZeroReject
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val isZero = expZero && manZero
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val isSubnormal = expZero && !manZero
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@ -303,24 +328,55 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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val isNan = expOne && !manZero
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val isQuiet = f32Mantissa.msb
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val subnormal = new Area{
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val manTop = Reg(UInt(log2Up(p.internalMantissaSize) bits))
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val shift = isSubnormal ? manTop | U(0)
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val counter = Reg(UInt(log2Up(p.internalMantissaSize+1) bits))
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val done, boot = Reg(Bool())
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when(isSubnormal && !done){
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busy := True
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when(boot){
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manTop := OHToUInt(OHMasking.first((f32Mantissa).reversed))
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boot := False
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} otherwise {
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input.value.mantissa.getDrivingReg := input.value.mantissa |<< 1
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counter := counter + 1
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when(counter === shift) {
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done := True
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}
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}
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}
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val expOffset = (UInt(p.internalExponentSize bits))
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expOffset := 0
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when(isSubnormal){
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expOffset := manTop.resized
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}
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when(!input.isStall){
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counter := 0
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done := False
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boot := True
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}
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}
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val recoded = p.internalFloating()
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recoded.mantissa := f32Mantissa
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recoded.exponent := f32Exponent
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recoded.exponent := (f32Exponent -^ subnormal.expOffset + (exponentOne - 127)).resized
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recoded.sign := f32Sign
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recoded.setNormal
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when(isZero){recoded.setZero}
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when(isSubnormal){recoded.setSubnormal}
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//when(isSubnormal){recoded.setSubnormal}
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when(isInfinity){recoded.setInfinity}
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when(isNan){recoded.setNan}
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val output = input.haltWhen(hazard).swapPayload(WriteInput())
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filtred.foreach(_.ready := False)
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feed.ready := input.valid && output.ready
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val output = input.haltWhen(busy).swapPayload(WriteInput())
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output.source := input.source
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output.lockId := input.lockId
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output.rd := input.rd
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output.value := recoded
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}
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}
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val shortPip = new Area{
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val input = decode.shortPip.stage()
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@ -330,23 +386,62 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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val result = p.storeLoadType().assignDontCare()
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val recoded = CombInit(input.rs1)
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when(recoded.special){
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switch(input.rs1.exponent(1 downto 0)){
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is(FpuFloat.ZERO){
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recoded.mantissa.clearAll()
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recoded.exponent.clearAll()
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val halt = False
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val recodedResult = Bits(32 bits)//recoded.asBits.resize(32 bits)
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val f32 = new Area{
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val exp = (recoded.exponent - (exponentOne-127)).resize(8 bits)
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val man = recoded.mantissa
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}
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is(FpuFloat.INFINITY){
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recoded.mantissa.clearAll()
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recoded.exponent.setAll()
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}
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is(FpuFloat.NAN){
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recoded.exponent.setAll()
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recodedResult := recoded.sign ## f32.exp ## f32.man
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val subnormal = new Area{
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val isSubnormal = !recoded.special && recoded.exponent <= exponentOne - 127
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val manTop = Reg(UInt(log2Up(p.internalMantissaSize) bits))
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val shift = isSubnormal ? manTop | U(0)
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val counter = Reg(UInt(log2Up(p.internalMantissaSize+1) bits))
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val done, boot = Reg(Bool())
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when(isSubnormal && !done){
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halt := True
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when(boot){
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manTop := (U(exponentOne - 127) - recoded.exponent).resized
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boot := False
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} otherwise {
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recoded.mantissa.getDrivingReg := (U(counter === 0) @@ recoded.mantissa) >> 1
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counter := counter + 1
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when(counter === shift) {
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done := True
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}
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}
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}
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when(isSubnormal){
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f32.exp := 0
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}
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when(!input.isStall){
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counter := 0
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done := False
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boot := True
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}
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}
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when(recoded.special){
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switch(input.rs1.exponent(1 downto 0)){
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is(FpuFloat.ZERO){
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recodedResult(0,23 bits).clearAll()
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recodedResult(23, 8 bits).clearAll()
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}
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is(FpuFloat.INFINITY){
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recodedResult(0, 23 bits).clearAll()
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recodedResult(23, 8 bits).setAll()
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}
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is(FpuFloat.NAN){
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recodedResult(23, 8 bits).setAll()
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}
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}
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}
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val recodedResult = recoded.asBits.resize(32 bits)
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val f2iShift = input.rs1.exponent - U(exponentOne)
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val f2iShifted = (U"1" @@ input.rs1.mantissa) << (f2iShift.resize(5 bits))
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@ -367,32 +462,33 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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3 -> (!rs1AbsSmaller && !rs1Equal)
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)
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val rawToFpu = new Area{
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val f32Mantissa = input.value(0, 23 bits).asUInt
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val f32Exponent = input.value(23, 8 bits).asUInt
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val f32Sign = input.value(31)
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val expZero = f32Exponent === 0
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val expOne = f32Exponent === 255
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val manZero = f32Mantissa === 0
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val isZero = expZero && manZero
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val isSubnormal = expZero && !manZero
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val isNormal = !expOne && !expZero
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val isInfinity = expOne && manZero
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val isNan = expOne && !manZero
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val isQuiet = f32Mantissa.msb
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val recoded = p.internalFloating()
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recoded.mantissa := f32Mantissa
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recoded.exponent := f32Exponent
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recoded.sign := f32Sign
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recoded.setNormal
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when(isZero){recoded.setZero}
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when(isSubnormal){recoded.setSubnormal}
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when(isInfinity){recoded.setInfinity}
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when(isNan){recoded.setNan}
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}
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//TODO
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// val rawToFpu = new Area{
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// val f32Mantissa = input.value(0, 23 bits).asUInt
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// val f32Exponent = input.value(23, 8 bits).asUInt
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// val f32Sign = input.value(31)
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//
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// val expZero = f32Exponent === 0
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// val expOne = f32Exponent === 255
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// val manZero = f32Mantissa === 0
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//
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// val isZero = expZero && manZero
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// val isSubnormal = expZero && !manZero
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// val isNormal = !expOne && !expZero
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// val isInfinity = expOne && manZero
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// val isNan = expOne && !manZero
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// val isQuiet = f32Mantissa.msb
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//
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// val recoded = p.internalFloating()
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// recoded.mantissa := f32Mantissa
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// recoded.exponent := f32Exponent
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// recoded.sign := f32Sign
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// recoded.setNormal
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// when(isZero){recoded.setZero}
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// when(isSubnormal){recoded.setSubnormal}
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// when(isInfinity){recoded.setInfinity}
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// when(isNan){recoded.setNan}
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// }
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val minMaxResult = (rs1Smaller ^ input.arg(0)) ? input.rs1 | input.rs2
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val cmpResult = B(rs1Smaller && !input.arg(1) || rs1Equal && !input.arg(0))
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@ -401,10 +497,10 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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val decoded = input.rs1.decode()
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fclassResult(0) := input.rs1.sign && decoded.isInfinity
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fclassResult(1) := input.rs1.sign && decoded.isNormal
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fclassResult(2) := input.rs1.sign && decoded.isSubnormal
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// fclassResult(2) := input.rs1.sign && decoded.isSubnormal //TODO
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fclassResult(3) := input.rs1.sign && decoded.isZero
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fclassResult(4) := !input.rs1.sign && decoded.isZero
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fclassResult(5) := !input.rs1.sign && decoded.isSubnormal
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// fclassResult(5) := !input.rs1.sign && decoded.isSubnormal //TODO
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fclassResult(6) := !input.rs1.sign && decoded.isNormal
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fclassResult(7) := !input.rs1.sign && decoded.isInfinity
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fclassResult(8) := decoded.isNan && !decoded.isQuiet
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@ -419,9 +515,9 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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is(FpuOpcode.FCLASS) { result := fclassResult.resized }
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}
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val toFpuRf = List(FpuOpcode.MIN_MAX, FpuOpcode.I2F, FpuOpcode.SGNJ, FpuOpcode.FMV_W_X).map(input.opcode === _).orR
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val toFpuRf = List(FpuOpcode.MIN_MAX, FpuOpcode.I2F, FpuOpcode.SGNJ).map(input.opcode === _).orR
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rfOutput.valid := input.valid && toFpuRf
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rfOutput.valid := input.valid && toFpuRf && !halt
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rfOutput.source := input.source
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rfOutput.lockId := input.lockId
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rfOutput.rd := input.rd
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@ -442,15 +538,12 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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rfOutput.value.mantissa := input.rs1.mantissa
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rfOutput.value.special := False //TODO
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}
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is(FpuOpcode.FMV_W_X){
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rfOutput.value := rawToFpu.recoded
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}
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}
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input.ready := (toFpuRf ? rfOutput.ready | io.port.map(_.rsp.ready).read(input.source))
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input.ready := !halt && (toFpuRf ? rfOutput.ready | io.port.map(_.rsp.ready).read(input.source))
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for(i <- 0 until portCount){
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def rsp = io.port(i).rsp
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rsp.valid := input.valid && input.source === i && !toFpuRf
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rsp.valid := input.valid && input.source === i && !toFpuRf && !halt
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rsp.value := result
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completion(i).increments += (RegNext(rsp.fire) init(False))
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}
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@ -463,7 +556,6 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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val mulA = U(input.msb1) @@ input.rs1.mantissa
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val mulB = U(input.msb2) @@ input.rs2.mantissa
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val mulC = mulA * mulB
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val expOffset = ((1 << p.internalExponentSize - 1) - 1)
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val exp = input.rs1.exponent +^ input.rs2.exponent
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}
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@ -478,13 +570,13 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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val man = needShift ? mulRounded(1, p.internalMantissaSize bits) | mulRounded(0, p.internalMantissaSize bits)
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val forceZero = input.rs1.isZeroOrSubnormal || input.rs2.isZeroOrSubnormal
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val forceUnderflow = exp <= math.expOffset
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val forceOverflow = exp > math.expOffset+254 || input.rs1.isInfinity || input.rs2.isInfinity
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val forceUnderflow = exp <= exponentOne + exponentOne - 127 - 23 // 0x6A //TODO
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val forceOverflow = exp > exponentOne + exponentOne + 127 || input.rs1.isInfinity || input.rs2.isInfinity
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val forceNan = input.rs1.isNan || input.rs2.isNan || ((input.rs1.isInfinity || input.rs2.isInfinity) && (input.rs1.isZero || input.rs2.isZero))
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val output = FpuFloat(p.internalExponentSize, p.internalMantissaSize)
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output.sign := input.rs1.sign ^ input.rs2.sign
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output.exponent := (exp - math.expOffset).resized
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output.exponent := (exp - exponentOne).resized
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output.mantissa := man
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output.setNormal
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@ -702,7 +794,7 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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val shifter = new Area {
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val exp21 = input.rs2.exponent -^ input.rs1.exponent
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val rs1ExponentBigger = exp21.msb || input.rs2.isZeroOrSubnormal
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val rs1ExponentBigger = (exp21.msb || input.rs2.isZeroOrSubnormal) && !input.rs1.isZeroOrSubnormal
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val rs1ExponentEqual = input.rs1.exponent === input.rs2.exponent
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val rs1MantissaBigger = input.rs1.mantissa > input.rs2.mantissa
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val absRs1Bigger = ((rs1ExponentBigger || rs1ExponentEqual && rs1MantissaBigger) && !input.rs1.isZeroOrSubnormal || input.rs1.isInfinity) && !input.rs2.isInfinity
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@ -746,7 +838,7 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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val exponent = xyExponent -^ shift + 1
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xySign clearWhen(input.rs1.isZeroOrSubnormal && input.rs2.isZeroOrSubnormal)
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val forceZero = xyMantissa === 0 || exponent.msb || (input.rs1.isZeroOrSubnormal && input.rs2.isZeroOrSubnormal)
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val forceOverflow = exponent(7 downto 0) === 255 || (input.rs1.isInfinity || input.rs2.isInfinity)
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val forceOverflow = exponent === exponentOne + 128 || (input.rs1.isInfinity || input.rs2.isInfinity)
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val forceNan = input.rs1.isNan || input.rs2.isNan || (input.rs1.isInfinity && input.rs2.isInfinity && (input.rs1.sign ^ input.rs2.sign))
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}
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@ -773,8 +865,28 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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}
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// val format = new Area{
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// val input = pipeArbiter.arbitrated.combStage()
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//
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// val rotate = new Area{
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// val input = Bits(p.internalMantissaSize bits)
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// val shift = UInt(log2Up(p.internalMantissaSize) bits)
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// val output = input.rotateLeft(shift)
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// }
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//
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// val decode = new Area{
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// val sign = input.raw(31)
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// val exp = input.raw(23, 8 bits).asUInt
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// val man = input.raw(23, 8 bits).asUInt
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// val isSubnormal = exp === 0 //zero ?
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// val manTop = OHToUInt(OHMasking.first((man ## U"1").reversed))
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// val shift = isSubnormal ? manTop | U(0)
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// rotate.shift := shift
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// }
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// }
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val write = new Area{
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val arbitrated = StreamArbiterFactory.lowerFirst.noLock.on(List(load.output, add.output, mul.output, shortPip.rfOutput))
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val arbitrated = StreamArbiterFactory.lowerFirst.noLock.on(List(load.s1.output, add.output, mul.output, shortPip.rfOutput))
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val isCommited = rf.lock.map(_.commited).read(arbitrated.lockId)
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val commited = arbitrated.haltWhen(!isCommited).toFlow
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@ -794,8 +906,8 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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port.data := commited.value
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when(port.valid){
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assert(!(port.data.exponent === 0 && !port.data.special))
|
||||
assert(!(port.data.exponent === port.data.exponent.maxValue && !port.data.special))
|
||||
assert(!(port.data.exponent === 0 && !port.data.special), "Special violation")
|
||||
assert(!(port.data.exponent === port.data.exponent.maxValue && !port.data.special), "Special violation")
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -831,11 +943,47 @@ object FpuSynthesisBench extends App{
|
|||
SpinalVerilog(new Component{
|
||||
val a = in UInt(width bits)
|
||||
val sel = in UInt(log2Up(width) bits)
|
||||
val result = out(a.rotateLeft(sel))
|
||||
val result = out(Delay(Delay(a,3).rotateLeft(Delay(sel,3)),3))
|
||||
setDefinitionName(Rotate.this.getName())
|
||||
})
|
||||
}
|
||||
|
||||
// rotate2_24 ->
|
||||
// Artix 7 -> 233 Mhz 96 LUT 167 FF
|
||||
// Artix 7 -> 420 Mhz 86 LUT 229 FF
|
||||
// rotate2_32 ->
|
||||
// Artix 7 -> 222 Mhz 108 LUT 238 FF
|
||||
// Artix 7 -> 399 Mhz 110 LUT 300 FF
|
||||
// rotate2_52 ->
|
||||
// Artix 7 -> 195 Mhz 230 LUT 362 FF
|
||||
// Artix 7 -> 366 Mhz 225 LUT 486 FF
|
||||
// rotate2_64 ->
|
||||
// Artix 7 -> 182 Mhz 257 LUT 465 FF
|
||||
// Artix 7 -> 359 Mhz 266 LUT 591 FF
|
||||
class Rotate2(width : Int) extends Rtl{
|
||||
override def getName(): String = "rotate2_" + width
|
||||
override def getRtlPath(): String = getName() + ".v"
|
||||
SpinalVerilog(new Component{
|
||||
val a = in UInt(width bits)
|
||||
val sel = in UInt(log2Up(width) bits)
|
||||
val result = out(Delay((U(0, width bits) @@ Delay(a,3)).rotateLeft(Delay(sel,3)),3))
|
||||
setDefinitionName(Rotate2.this.getName())
|
||||
})
|
||||
}
|
||||
|
||||
class Rotate3(width : Int) extends Rtl{
|
||||
override def getName(): String = "rotate3_" + width
|
||||
override def getRtlPath(): String = getName() + ".v"
|
||||
SpinalVerilog(new Component{
|
||||
val a = Delay(in UInt(width bits), 3)
|
||||
val sel = Delay(in UInt(log2Up(width) bits),3)
|
||||
// val result =
|
||||
// val output = Delay(result, 3)
|
||||
setDefinitionName(Rotate3.this.getName())
|
||||
})
|
||||
}
|
||||
|
||||
|
||||
val rtls = ArrayBuffer[Rtl]()
|
||||
// rtls += new Fpu(
|
||||
// "32",
|
||||
|
|
@ -858,10 +1006,14 @@ object FpuSynthesisBench extends App{
|
|||
// rtls += new Shifter(32)
|
||||
// rtls += new Shifter(52)
|
||||
// rtls += new Shifter(64)
|
||||
rtls += new Rotate(24)
|
||||
rtls += new Rotate(32)
|
||||
rtls += new Rotate(52)
|
||||
rtls += new Rotate(64)
|
||||
// rtls += new Rotate(24)
|
||||
// rtls += new Rotate(32)
|
||||
// rtls += new Rotate(52)
|
||||
// rtls += new Rotate(64)
|
||||
rtls += new Rotate3(24)
|
||||
rtls += new Rotate3(32)
|
||||
rtls += new Rotate3(52)
|
||||
rtls += new Rotate3(64)
|
||||
|
||||
val targets = XilinxStdTargets()// ++ AlteraStdTargets()
|
||||
|
||||
|
|
|
|||
|
|
@ -50,14 +50,14 @@ case class FpuFloat(exponentSize: Int,
|
|||
|
||||
def isNormal = !special
|
||||
def isZero = special && exponent(1 downto 0) === 0
|
||||
def isSubnormal = special && exponent(1 downto 0) === 1
|
||||
//def isSubnormal = special && exponent(1 downto 0) === 1
|
||||
def isInfinity = special && exponent(1 downto 0) === 2
|
||||
def isNan = special && exponent(1 downto 0) === 3
|
||||
def isQuiet = mantissa.msb
|
||||
|
||||
def setNormal = { special := False }
|
||||
def setZero = { special := True; exponent(1 downto 0) := 0 }
|
||||
def setSubnormal = { special := True; exponent(1 downto 0) := 1 }
|
||||
//def setSubnormal = { special := True; exponent(1 downto 0) := 1 }
|
||||
def setInfinity = { special := True; exponent(1 downto 0) := 2 }
|
||||
def setNan = { special := True; exponent(1 downto 0) := 3 }
|
||||
def setNanQuiet = { special := True; exponent(1 downto 0) := 3; mantissa.msb := True }
|
||||
|
|
@ -65,7 +65,7 @@ case class FpuFloat(exponentSize: Int,
|
|||
def decode() = {
|
||||
val ret = FpuFloatDecoded()
|
||||
ret.isZero := isZero
|
||||
ret.isSubnormal := isSubnormal
|
||||
//ret.isSubnormal := isSubnormal
|
||||
ret.isNormal := isNormal
|
||||
ret.isInfinity := isInfinity
|
||||
ret.isNan := isNan
|
||||
|
|
@ -101,7 +101,7 @@ case class FpuParameter( internalMantissaSize : Int,
|
|||
withDouble : Boolean){
|
||||
|
||||
val storeLoadType = HardType(Bits(if(withDouble) 64 bits else 32 bits))
|
||||
val internalExponentSize = if(withDouble) 11 else 8
|
||||
val internalExponentSize = (if(withDouble) 11 else 8) + 1
|
||||
val internalFloating = HardType(FpuFloat(exponentSize = internalExponentSize, mantissaSize = internalMantissaSize))
|
||||
|
||||
val rfAddress = HardType(UInt(5 bits))
|
||||
|
|
@ -132,7 +132,7 @@ case class FpuCmd(p : FpuParameter) extends Bundle{
|
|||
|
||||
case class FpuCommit(p : FpuParameter) extends Bundle{
|
||||
val write = Bool()
|
||||
val load = Bool()
|
||||
val sync = Bool()
|
||||
val value = p.storeLoadType() // IEEE 754
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -11,7 +11,8 @@ class FpuPlugin(externalFpu : Boolean = false,
|
|||
|
||||
object FPU_ENABLE extends Stageable(Bool())
|
||||
object FPU_COMMIT extends Stageable(Bool())
|
||||
object FPU_LOAD extends Stageable(Bool())
|
||||
object FPU_COMMIT_SYNC extends Stageable(Bool())
|
||||
object FPU_COMMIT_LOAD extends Stageable(Bool())
|
||||
object FPU_RSP extends Stageable(Bool())
|
||||
object FPU_FORKED extends Stageable(Bool())
|
||||
object FPU_OPCODE extends Stageable(FpuOpcode())
|
||||
|
|
@ -28,7 +29,6 @@ class FpuPlugin(externalFpu : Boolean = false,
|
|||
FPU_ENABLE -> True,
|
||||
FPU_COMMIT -> False,
|
||||
FPU_RSP -> True,
|
||||
FPU_LOAD -> False,
|
||||
REGFILE_WRITE_VALID -> True,
|
||||
BYPASSABLE_EXECUTE_STAGE -> False,
|
||||
BYPASSABLE_MEMORY_STAGE -> False
|
||||
|
|
@ -37,8 +37,7 @@ class FpuPlugin(externalFpu : Boolean = false,
|
|||
val floatRfWrite = List[ENC](
|
||||
FPU_ENABLE -> True,
|
||||
FPU_COMMIT -> True,
|
||||
FPU_RSP -> False,
|
||||
FPU_LOAD -> False
|
||||
FPU_RSP -> False
|
||||
)
|
||||
|
||||
val addSub = floatRfWrite :+ FPU_OPCODE -> FpuOpcode.ADD
|
||||
|
|
@ -60,7 +59,6 @@ class FpuPlugin(externalFpu : Boolean = false,
|
|||
FPU_ENABLE -> True,
|
||||
FPU_OPCODE -> FpuOpcode.LOAD,
|
||||
FPU_COMMIT -> True,
|
||||
FPU_LOAD -> True,
|
||||
FPU_RSP -> False
|
||||
)
|
||||
|
||||
|
|
@ -68,7 +66,6 @@ class FpuPlugin(externalFpu : Boolean = false,
|
|||
FPU_ENABLE -> True,
|
||||
FPU_OPCODE -> FpuOpcode.STORE,
|
||||
FPU_COMMIT -> False,
|
||||
FPU_LOAD -> False,
|
||||
FPU_RSP -> True
|
||||
)
|
||||
|
||||
|
|
@ -164,7 +161,7 @@ class FpuPlugin(externalFpu : Boolean = false,
|
|||
//Maybe it might be better to not fork before fire to avoid RF stall on commits
|
||||
val forked = Reg(Bool) setWhen(port.cmd.fire) clearWhen(!arbitration.isStuck) init(False)
|
||||
|
||||
val intRfReady = Reg(Bool()) setWhen(!arbitration.isStuckByOthers) clearWhen(!arbitration.isStuck)
|
||||
val intRfReady = Reg(Bool()) setWhen(!arbitration.isStuckByOthers) clearWhen(!arbitration.isStuck) //TODO is that still in use ?
|
||||
val hazard = (input(RS1_USE) && !intRfReady) || csr.pendings.msb || csr.csrActive
|
||||
|
||||
arbitration.haltItself setWhen(arbitration.isValid && input(FPU_ENABLE) && hazard)
|
||||
|
|
@ -181,6 +178,9 @@ class FpuPlugin(externalFpu : Boolean = false,
|
|||
port.cmd.format := FpuFormat.FLOAT
|
||||
|
||||
insert(FPU_FORKED) := forked || port.cmd.fire
|
||||
|
||||
insert(FPU_COMMIT_SYNC) := List(FpuOpcode.LOAD, FpuOpcode.FMV_W_X).map(_ === input(FPU_OPCODE)).orR
|
||||
insert(FPU_COMMIT_LOAD) := input(FPU_OPCODE) === FpuOpcode.LOAD
|
||||
}
|
||||
|
||||
writeBack plug new Area{
|
||||
|
|
@ -206,9 +206,9 @@ class FpuPlugin(externalFpu : Boolean = false,
|
|||
// Manage $load
|
||||
val commit = Stream(FpuCommit(p))
|
||||
commit.valid := isCommit && arbitration.isMoving
|
||||
commit.value.assignFromBits(output(DBUS_DATA))
|
||||
commit.value := (input(FPU_COMMIT_LOAD) ? output(DBUS_DATA) | input(RS1))
|
||||
commit.write := arbitration.isValid
|
||||
commit.load := input(FPU_LOAD)
|
||||
commit.sync := input(FPU_COMMIT_SYNC)
|
||||
|
||||
when(arbitration.isValid && !commit.ready){
|
||||
arbitration.haltByOther := True
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@ class FpuTest extends FunSuite{
|
|||
val b2f = lang.Float.intBitsToFloat(_)
|
||||
val f2b = lang.Float.floatToIntBits(_)
|
||||
def clamp(f : Float) = {
|
||||
if(f.abs < b2f(0x00800000)) b2f(f2b(f) & 0x80000000) else f
|
||||
f // if(f.abs < b2f(0x00800000)) b2f(f2b(f) & 0x80000000) else f
|
||||
}
|
||||
|
||||
test("directed"){
|
||||
|
|
@ -74,7 +74,7 @@ class FpuTest extends FunSuite{
|
|||
commitQueue += {cmd =>
|
||||
cmd.write #= true
|
||||
cmd.value #= value
|
||||
cmd.load #= true
|
||||
cmd.sync #= true
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -112,7 +112,7 @@ class FpuTest extends FunSuite{
|
|||
}
|
||||
commitQueue += {cmd =>
|
||||
cmd.write #= true
|
||||
cmd.load #= false
|
||||
cmd.sync #= false
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -128,7 +128,7 @@ class FpuTest extends FunSuite{
|
|||
}
|
||||
commitQueue += {cmd =>
|
||||
cmd.write #= true
|
||||
cmd.load #= false
|
||||
cmd.sync #= false
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -144,7 +144,7 @@ class FpuTest extends FunSuite{
|
|||
}
|
||||
commitQueue += {cmd =>
|
||||
cmd.write #= true
|
||||
cmd.load #= false
|
||||
cmd.sync #= false
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -160,7 +160,7 @@ class FpuTest extends FunSuite{
|
|||
}
|
||||
commitQueue += {cmd =>
|
||||
cmd.write #= true
|
||||
cmd.load #= false
|
||||
cmd.sync #= false
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -176,7 +176,7 @@ class FpuTest extends FunSuite{
|
|||
}
|
||||
commitQueue += {cmd =>
|
||||
cmd.write #= true
|
||||
cmd.load #= false
|
||||
cmd.sync #= false
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -219,7 +219,7 @@ class FpuTest extends FunSuite{
|
|||
}
|
||||
commitQueue += {cmd =>
|
||||
cmd.write #= true
|
||||
cmd.load #= false
|
||||
cmd.sync #= false
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -239,7 +239,7 @@ class FpuTest extends FunSuite{
|
|||
def fmv_w_x(rd : Int, value : Int): Unit ={
|
||||
cmdQueue += {cmd =>
|
||||
cmd.opcode #= cmd.opcode.spinalEnum.FMV_W_X
|
||||
cmd.value #= value.toLong & 0xFFFFFFFFl
|
||||
cmd.value.randomize()
|
||||
cmd.rs1.randomize()
|
||||
cmd.rs2.randomize()
|
||||
cmd.rs3.randomize()
|
||||
|
|
@ -248,7 +248,8 @@ class FpuTest extends FunSuite{
|
|||
}
|
||||
commitQueue += {cmd =>
|
||||
cmd.write #= true
|
||||
cmd.load #= false
|
||||
cmd.sync #= true
|
||||
cmd.value #= value.toLong & 0xFFFFFFFFl
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -264,7 +265,7 @@ class FpuTest extends FunSuite{
|
|||
}
|
||||
commitQueue += {cmd =>
|
||||
cmd.write #= true
|
||||
cmd.load #= false
|
||||
cmd.sync #= false
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -281,7 +282,7 @@ class FpuTest extends FunSuite{
|
|||
}
|
||||
commitQueue += {cmd =>
|
||||
cmd.write #= true
|
||||
cmd.load #= false
|
||||
cmd.sync #= false
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -309,11 +310,12 @@ class FpuTest extends FunSuite{
|
|||
}
|
||||
}
|
||||
def checkFloat(ref : Float, dut : Float): Boolean ={
|
||||
if(ref.signum != dut.signum) return false
|
||||
if((f2b(ref) & 0x80000000) != (f2b(dut) & 0x80000000)) return false
|
||||
if(ref == 0.0 && dut == 0.0 && f2b(ref) != f2b(dut)) return false
|
||||
if(ref.isNaN && dut.isNaN) return true
|
||||
if(ref == dut) return true
|
||||
if(ref.abs * 1.0001 > dut.abs && ref.abs * 0.9999 < dut.abs && ref.signum == dut.signum) return true
|
||||
if(ref.abs * 1.0001 + Float.MinPositiveValue >= dut.abs && ref.abs * 0.9999 - Float.MinPositiveValue <= dut.abs) return true
|
||||
// if(ref + Float.MinPositiveValue*2.0f === dut || dut + Float.MinPositiveValue*2.0f === ref)
|
||||
false
|
||||
}
|
||||
def checkFloatExact(ref : Float, dut : Float): Boolean ={
|
||||
|
|
@ -346,6 +348,16 @@ class FpuTest extends FunSuite{
|
|||
}
|
||||
}
|
||||
|
||||
def testLoadStore(a : Float): Unit ={
|
||||
val rd = Random.nextInt(32)
|
||||
load(rd, a)
|
||||
storeFloat(rd){v =>
|
||||
val refUnclamped = a
|
||||
val ref = a
|
||||
println(f"$a = $v, $ref")
|
||||
assert(f2b(v) == f2b(ref))
|
||||
}
|
||||
}
|
||||
def testMul(a : Float, b : Float): Unit ={
|
||||
val rs = new RegAllocator()
|
||||
val rs1, rs2, rs3 = rs.allocate()
|
||||
|
|
@ -515,7 +527,7 @@ class FpuTest extends FunSuite{
|
|||
|
||||
def withMinus(that : Seq[Float]) = that.flatMap(f => List(f, -f))
|
||||
val fZeros = withMinus(List(0.0f))
|
||||
val fSubnormals = withMinus(List(b2f(0x00000000+1), b2f(0x00000000+2), b2f(0x00800000-2), b2f(0x00800000-1)))
|
||||
val fSubnormals = withMinus(List(b2f(0x00000000+1), b2f(0x00000000+2), b2f(0x00006800), b2f(0x00800000-2), b2f(0x00800000-1)))
|
||||
val fExpSmall = withMinus(List(b2f(0x00800000), b2f(0x00800000+1), b2f(0x00800000 + 2)))
|
||||
val fExpNormal = withMinus(List(b2f(0x3f800000-2), b2f(0x3f800000-1), b2f(0x3f800000), b2f(0x3f800000+1), b2f(0x3f800000+2)))
|
||||
val fExpBig = withMinus(List(b2f(0x7f7fffff-2), b2f(0x7f7fffff-1), b2f(0x7f7fffff)))
|
||||
|
|
@ -533,13 +545,6 @@ class FpuTest extends FunSuite{
|
|||
|
||||
|
||||
|
||||
testMul(1.2f, 0f)
|
||||
for(a <- fAll; _ <- 0 until 50) testMul(a, randomFloat())
|
||||
for(b <- fAll; _ <- 0 until 50) testMul(randomFloat(), b)
|
||||
for(a <- fAll; b <- fAll) testMul(a, b)
|
||||
for(_ <- 0 until 1000) testMul(randomFloat(), randomFloat())
|
||||
|
||||
|
||||
testAdd(b2f(0x3f800000), b2f(0x3f800000-1))
|
||||
testAdd(1.1f, 2.3f)
|
||||
testAdd(1.2f, -1.2f)
|
||||
|
|
@ -555,6 +560,28 @@ class FpuTest extends FunSuite{
|
|||
for(a <- fAll; b <- fAll) testAdd(a, b)
|
||||
for(_ <- 0 until 1000) testAdd(randomFloat(), randomFloat())
|
||||
|
||||
testLoadStore(1.2f)
|
||||
testMul(1.2f, 2.5f)
|
||||
testMul(b2f(0x00400000), 16.0f)
|
||||
testMul(b2f(0x00100000), 16.0f)
|
||||
testMul(b2f(0x00180000), 16.0f)
|
||||
testMul(b2f(0x00000004), 16.0f)
|
||||
testMul(b2f(0x00000040), 16.0f)
|
||||
testMul(b2f(0x00000041), 16.0f)
|
||||
testMul(b2f(0x00000001), b2f(0x00000001))
|
||||
testMul(1.0f, b2f(0x00000001))
|
||||
testMul(0.5f, b2f(0x00000001))
|
||||
|
||||
// dut.clockDomain.waitSampling(1000)
|
||||
// simSuccess()
|
||||
|
||||
testMul(1.2f, 0f)
|
||||
for(a <- fAll; _ <- 0 until 50) testMul(a, randomFloat())
|
||||
for(b <- fAll; _ <- 0 until 50) testMul(randomFloat(), b)
|
||||
for(a <- fAll; b <- fAll) testMul(a, b)
|
||||
for(_ <- 0 until 1000) testMul(randomFloat(), randomFloat())
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue