Add decodePcGen
This commit is contained in:
Dolu1990
parent
1fb138de1f
commit
f872d599e2
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@ -160,7 +160,8 @@ class IBusSimplePlugin(interfaceKeepData : Boolean, catchAccessFault : Boolean,
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var prefetchExceptionPort : Flow[ExceptionCause] = null
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def resetVector = BigInt(0x80000000l)
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def keepPcPlus4 = false
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def decodePcGen = true
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def compressedGen = true
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lazy val fetcherHalt = False
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lazy val decodeNextPcValid = Bool
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lazy val decodeNextPc = UInt(32 bits)
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@ -191,7 +192,25 @@ class IBusSimplePlugin(interfaceKeepData : Boolean, catchAccessFault : Boolean,
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import pipeline.config._
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pipeline plug new Area {
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val pcCalc = new Area {
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//JumpService hardware implementation
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val jump = new Area {
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val sortedByStage = jumpInfos.sortWith((a, b) => {
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(pipeline.indexOf(a.stage) > pipeline.indexOf(b.stage)) ||
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(pipeline.indexOf(a.stage) == pipeline.indexOf(b.stage) && a.priority > b.priority)
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})
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val valids = sortedByStage.map(_.interface.valid)
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val pcs = sortedByStage.map(_.interface.payload)
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val pcLoad = Flow(UInt(32 bits))
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pcLoad.valid := jumpInfos.map(_.interface.valid).orR
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pcLoad.payload := MuxOH(OHMasking.first(valids.asBits), pcs)
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}
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def flush = jump.pcLoad.valid
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val fetchPc = new Area {
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val output = Stream(UInt(32 bits))
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//PC calculation without Jump
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@ -202,35 +221,34 @@ class IBusSimplePlugin(interfaceKeepData : Boolean, catchAccessFault : Boolean,
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pcReg := pcPlus4
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}
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//JumpService hardware implementation
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val jump = new Area {
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val sortedByStage = jumpInfos.sortWith((a, b) => {
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(pipeline.indexOf(a.stage) > pipeline.indexOf(b.stage)) ||
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(pipeline.indexOf(a.stage) == pipeline.indexOf(b.stage) && a.priority > b.priority)
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})
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val valids = sortedByStage.map(_.interface.valid)
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val pcs = sortedByStage.map(_.interface.payload)
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val pcLoad = Flow(UInt(32 bits))
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pcLoad.valid := jumpInfos.map(_.interface.valid).orR
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pcLoad.payload := MuxOH(OHMasking.first(valids.asBits), pcs)
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//application of the selected jump request
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when(pcLoad.valid) {
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pcReg := pcLoad.payload
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}
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//application of the selected jump request
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when(jump.pcLoad.valid) {
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pcReg := jump.pcLoad.payload
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}
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output.valid := (RegNext(True) init (False)) // && !jump.pcLoad.valid
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output.payload := pcReg
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}
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def flush = pcCalc.jump.pcLoad.valid
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val decodePc = ifGen(decodePcGen)(new Area {
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//PC calculation without Jump
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val pcReg = Reg(UInt(32 bits)) init (resetVector) addAttribute (Verilator.public)
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val pcPlus4 = pcReg + 4
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if (keepPcPlus4) KeepAttribute(pcPlus4)
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when(decode.arbitration.isFiring) {
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pcReg := pcPlus4
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}
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//application of the selected jump request
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when(jump.pcLoad.valid) {
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pcReg := jump.pcLoad.payload
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}
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})
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val iBusCmd = new Area {
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def input = pcCalc.output
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def input = fetchPc.output
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val output = input.continueWhen(iBus.cmd.fire)
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@ -272,16 +290,21 @@ class IBusSimplePlugin(interfaceKeepData : Boolean, catchAccessFault : Boolean,
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val injector = new Area {
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val inputBeforeHalt = iBusRsp.output.s2mPipe(flush)
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val inputBeforeHalt = iBusRsp.output//.s2mPipe(flush)
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val input = inputBeforeHalt.haltWhen(fetcherHalt)
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val stage = input.m2sPipe(flush || decode.arbitration.isRemoved)
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decodeNextPcValid := RegNext(inputBeforeHalt.isStall)
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decodeNextPc := decode.input(PC)
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if(decodePcGen){
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decodeNextPcValid := True
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decodeNextPc := decodePc.pcReg
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}else {
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decodeNextPcValid := RegNext(inputBeforeHalt.isStall)
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decodeNextPc := decode.input(PC)
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}
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stage.ready := !decode.arbitration.isStuck
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decode.arbitration.isValid := stage.valid
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decode.insert(PC) := stage.pc
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decode.insert(PC) := (if(decodePcGen) decodePc.pcReg else stage.pc)
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decode.insert(INSTRUCTION) := stage.rsp.inst
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decode.insert(INSTRUCTION_ANTICIPATED) := Mux(decode.arbitration.isStuck, decode.input(INSTRUCTION), input.rsp.inst)
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decode.insert(INSTRUCTION_READY) := True
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@ -295,67 +318,3 @@ class IBusSimplePlugin(interfaceKeepData : Boolean, catchAccessFault : Boolean,
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}
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}
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}
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//class IBusSimplePlugin(interfaceKeepData : Boolean, catchAccessFault : Boolean) extends Plugin[VexRiscv]{
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// var iBus : IBusSimpleBus = null
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//
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// object IBUS_ACCESS_ERROR extends Stageable(Bool)
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// var decodeExceptionPort : Flow[ExceptionCause] = null
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// override def setup(pipeline: VexRiscv): Unit = {
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// if(catchAccessFault) {
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// val exceptionService = pipeline.service(classOf[ExceptionService])
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// decodeExceptionPort = exceptionService.newExceptionPort(pipeline.decode,1)
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// }
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// }
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//
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// override def build(pipeline: VexRiscv): Unit = {
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// import pipeline._
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// import pipeline.config._
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// iBus = master(IBusSimpleBus(interfaceKeepData)).setName("iBus")
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// prefetch plug new Area {
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// val pendingCmd = RegInit(False) clearWhen (iBus.rsp.ready) setWhen (iBus.cmd.fire)
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//
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// //Emit iBus.cmd request
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// iBus.cmd.valid := prefetch.arbitration.isValid && !prefetch.arbitration.removeIt && !prefetch.arbitration.isStuckByOthers && !(pendingCmd && !iBus.rsp.ready) //prefetch.arbitration.isValid && !prefetch.arbitration.isStuckByOthers
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// iBus.cmd.pc := prefetch.output(PC)
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// prefetch.arbitration.haltItself setWhen (!iBus.cmd.ready || (pendingCmd && !iBus.rsp.ready))
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// }
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//
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// //Bus rsp buffer
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// val rspBuffer = if(!interfaceKeepData) new Area{
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// val valid = RegInit(False) setWhen(iBus.rsp.ready) clearWhen(!fetch.arbitration.isStuck)
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// val error = Reg(Bool)
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// val data = Reg(Bits(32 bits))
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// when(!valid) {
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// data := iBus.rsp.inst
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// error := iBus.rsp.error
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// }
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// } else null
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//
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// //Insert iBus.rsp into INSTRUCTION
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// fetch.insert(INSTRUCTION) := iBus.rsp.inst
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// fetch.insert(IBUS_ACCESS_ERROR) := iBus.rsp.error
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// if(!interfaceKeepData) {
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// when(rspBuffer.valid) {
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// fetch.insert(INSTRUCTION) := rspBuffer.data
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// fetch.insert(IBUS_ACCESS_ERROR) := rspBuffer.error
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// }
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// }
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//
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// fetch.insert(IBUS_ACCESS_ERROR) clearWhen(!fetch.arbitration.isValid) //Avoid interference with instruction injection from the debug plugin
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//
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// if(interfaceKeepData)
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// fetch.arbitration.haltItself setWhen(fetch.arbitration.isValid && !iBus.rsp.ready)
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// else
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// fetch.arbitration.haltItself setWhen(fetch.arbitration.isValid && !iBus.rsp.ready && !rspBuffer.valid)
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//
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// decode.insert(INSTRUCTION_ANTICIPATED) := Mux(decode.arbitration.isStuck,decode.input(INSTRUCTION),fetch.output(INSTRUCTION))
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// decode.insert(INSTRUCTION_READY) := True
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//
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// if(catchAccessFault){
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// decodeExceptionPort.valid := decode.arbitration.isValid && decode.input(IBUS_ACCESS_ERROR)
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// decodeExceptionPort.code := 1
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// decodeExceptionPort.badAddr := decode.input(PC)
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// }
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// }
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//}
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