#60 Fix MMU holding invalid tlb, while linux is assuming it isn't doing so.
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@ -135,6 +135,16 @@ class MmuPlugin(ioRange : UInt => Bool,
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port.bus.rsp.refilling := False
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}
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port.bus.rsp.isIoAccess := ioRange(port.bus.rsp.physicalAddress)
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// Avoid keeping any invalid line in the cache more than one memory translation.
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// https://github.com/riscv/riscv-linux/blob/8fe28cb58bcb235034b64cbbb7550a8a43fd88be/arch/riscv/include/asm/pgtable.h#L276
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when(port.bus.cmd.isValid && port.bus.end) {
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for (line <- cache) {
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when(line.valid && line.exception) {
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line.valid := False
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}
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}
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}
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}
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val shared = new Area {
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@ -241,7 +251,7 @@ class MmuPlugin(ioRange : UInt => Bool,
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execute plug new Area{
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import execute._
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val tlbWriteBuffer = Reg(UInt(20 bits))
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when(arbitration.isFiring && input(IS_SFENCE_VMA)){
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when(arbitration.isFiring && input(IS_SFENCE_VMA)){ // || csrService.isWriting(CSR.SATP)
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for(port <- core.ports; line <- port.cache) line.valid := False //Assume that the instruction already fetched into the pipeline are ok
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}
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}
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