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Merge pull request #71 from xobs/mmu-2-stage

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Mmu 2 stage
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Dolu1990 2019-04-26 14:25:29 +02:00 committed by GitHub
commit fa13e46e87
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3 changed files with 5 additions and 4 deletions
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2
src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
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@ -143,7 +143,7 @@ class DBusCachedPlugin(config : DataCacheConfig,
decoderService.add(FENCE, Nil)
mmuBus = pipeline.service(classOf[MemoryTranslator]).newTranslationPort(MemoryTranslatorPort.PRIORITY_DATA ,memoryTranslatorPortConfig)
redoBranch = pipeline.service(classOf[JumpService]).createJumpInterface(pipeline.writeBack)
redoBranch = pipeline.service(classOf[JumpService]).createJumpInterface(if(pipeline.writeBack != null) pipeline.writeBack else pipeline.execute)
if(catchSomething)
exceptionBus = pipeline.service(classOf[ExceptionService]).newExceptionPort(pipeline.writeBack)

2
src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
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@ -309,7 +309,7 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false,
if(memoryTranslatorPortConfig != null) {
mmuBus = pipeline.service(classOf[MemoryTranslator]).newTranslationPort(MemoryTranslatorPort.PRIORITY_DATA, memoryTranslatorPortConfig)
redoBranch = pipeline.service(classOf[JumpService]).createJumpInterface(pipeline.memory)
redoBranch = pipeline.service(classOf[JumpService]).createJumpInterface(if(pipeline.memory != null) pipeline.memory else pipeline.execute)
}
}

5
src/main/scala/vexriscv/plugin/MmuPlugin.scala
View file

@ -250,8 +250,9 @@ class MmuPlugin(ioRange : UInt => Bool,
}
}
writeBack plug new Area{
import writeBack._
val fenceStage = stages.last
fenceStage plug new Area{
import fenceStage._
when(arbitration.isValid && input(IS_SFENCE_VMA)){ // || csrService.isWriting(CSR.SATP)
for(port <- core.ports; line <- port.cache) line.valid := False //Assume that the instruction already fetched into the pipeline are ok
}