Merge branch 'debugPlugin' into dev
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commit
fa2899a1a2
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@ -56,6 +56,7 @@ trait InterruptionInhibitor{
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trait ExceptionInhibitor{
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def inhibateException() : Unit
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def inhibateEbreakException() : Unit
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}
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@ -32,6 +32,8 @@ object CsrAccess {
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object NONE extends CsrAccess
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}
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case class ExceptionPortInfo(port : Flow[ExceptionCause],stage : Stage, priority : Int)
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case class CsrPluginConfig(
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catchIllegalAccess : Boolean,
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@ -457,6 +459,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
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var allowInterrupts : Bool = null
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var allowException : Bool = null
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var allowEbreakException : Bool = null
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val csrMapping = new CsrMapping()
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@ -565,6 +568,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
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allowInterrupts = True
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allowException = True
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allowEbreakException = True
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for (i <- interruptSpecs) i.cond = i.cond.pull()
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@ -577,6 +581,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
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def inhibateInterrupts() : Unit = allowInterrupts := False
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def inhibateException() : Unit = allowException := False
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def inhibateEbreakException() : Unit = allowEbreakException := False
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override def isUser() : Bool = privilege === 0
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override def isSupervisor(): Bool = privilege === 1
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@ -1097,7 +1102,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
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}
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if(ebreakGen) when(arbitration.isValid && input(ENV_CTRL) === EnvCtrlEnum.EBREAK){
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if(ebreakGen) when(arbitration.isValid && input(ENV_CTRL) === EnvCtrlEnum.EBREAK && allowEbreakException){
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selfException.valid := True
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selfException.code := 3
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}
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@ -176,8 +176,6 @@ case class DebugExtensionIo() extends Bundle with IMasterSlave{
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}
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}
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class DebugPlugin(var debugClockDomain : ClockDomain, hardwareBreakpointCount : Int = 0) extends Plugin[VexRiscv] {
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var io : DebugExtensionIo = null
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@ -226,6 +224,10 @@ class DebugPlugin(var debugClockDomain : ClockDomain, hardwareBreakpointCount :
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val isPipBusy = RegNext(stages.map(_.arbitration.isValid).orR || iBusFetcher.incoming())
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val godmode = RegInit(False) setWhen(haltIt && !isPipBusy)
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val haltedByBreak = RegInit(False)
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val debugUsed = RegInit(False) setWhen(io.bus.cmd.valid) addAttribute(Verilator.public)
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val disableEbreak = RegInit(False)
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val allowEBreak = debugUsed && !disableEbreak
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val hardwareBreakpoints = Vec(Reg(new Bundle{
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val valid = Bool()
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@ -259,6 +261,7 @@ class DebugPlugin(var debugClockDomain : ClockDomain, hardwareBreakpointCount :
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haltIt setWhen (io.bus.cmd.data(17)) clearWhen (io.bus.cmd.data(25))
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haltedByBreak clearWhen (io.bus.cmd.data(25))
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godmode clearWhen(io.bus.cmd.data(25))
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disableEbreak setWhen (io.bus.cmd.data(18)) clearWhen (io.bus.cmd.data(26))
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}
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}
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is(0x1) {
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@ -277,8 +280,6 @@ class DebugPlugin(var debugClockDomain : ClockDomain, hardwareBreakpointCount :
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}
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}
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val allowEBreak = if(!pipeline.serviceExist(classOf[PrivilegeService])) True else pipeline.service(classOf[PrivilegeService]).isMachine()
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decode.insert(DO_EBREAK) := !haltIt && (decode.input(IS_EBREAK) || hardwareBreakpoints.map(hb => hb.valid && hb.pc === (decode.input(PC) >> 1)).foldLeft(False)(_ || _)) && allowEBreak
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when(execute.arbitration.isValid && execute.input(DO_EBREAK)){
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execute.arbitration.haltByOther := True
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@ -328,6 +329,12 @@ class DebugPlugin(var debugClockDomain : ClockDomain, hardwareBreakpointCount :
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}
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if(pipeline.things.contains(DEBUG_BYPASS_CACHE)) pipeline(DEBUG_BYPASS_CACHE) := True
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}
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when(allowEBreak) {
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pipeline.plugins.foreach {
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case p: ExceptionInhibitor => p.inhibateEbreakException()
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case _ =>
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}
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}
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val wakeService = serviceElse(classOf[IWake], null)
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if(wakeService != null) when(haltIt){
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@ -1673,6 +1673,7 @@ public:
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}
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#endif
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bool failed = false;
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try {
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// run simulation for 100 clock periods
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@ -3496,6 +3497,11 @@ public:
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if(clientSuccess) pass();
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if(clientFail) fail();
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}
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virtual void postReset(){
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Workspace::postReset();
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top->VexRiscv->DebugPlugin_debugUsed = 1;
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}
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};
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#endif
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