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VexRiscv
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Add pipelining option (hit 60 Mhz)

This commit is contained in:
Charles Papon 2017-07-29 02:52:03 +02:00
parent 3bdf020c67
commit fa887d3830
2 changed files with 72 additions and 45 deletions
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59
src/main/scala/vexriscv/demo/Murax.scala
View File

@ -28,13 +28,19 @@ import vexriscv.{plugin, VexRiscvConfig, VexRiscv}
case class MuraxConfig(coreFrequency : HertzNumber,
onChipRamSize : BigInt,
pipelineDBus : Boolean)
pipelineDBus : Boolean,
pipelineMainBus : Boolean,
pipelineApbBridge : Boolean){
require(pipelineApbBridge || pipelineMainBus, "At least pipelineMainBus or pipelineApbBridge should be enable to avoid wipe transactions")
}
object MuraxConfig{
def default = MuraxConfig(
coreFrequency = 12 MHz,
onChipRamSize = 8 kB,
pipelineDBus = false
pipelineDBus = false,
pipelineMainBus = true,
pipelineApbBridge = false
)
}
@ -213,10 +219,20 @@ case class Murax(config : MuraxConfig) extends Component{
iBus.cmd.ready := mainBus.cmd.ready && !dBus.cmd.valid
dBus.cmd.ready := mainBus.cmd.ready
val rspPending = RegInit(False) clearWhen(mainBus.rsp.valid)
val rspTarget = RegInit(False)
when(mainBus.cmd.fire){
rspTarget := dBus.cmd.valid
when(mainBus.cmd.fire && !mainBus.cmd.wr){
rspTarget := dBus.cmd.valid
rspPending := True
}
when(rspPending && !mainBus.rsp.valid){
iBus.cmd.ready := False
dBus.cmd.ready := False
mainBus.cmd.valid := False
}
iBus.rsp.ready := mainBus.rsp.valid && !rspTarget
iBus.rsp.inst := mainBus.rsp.data
iBus.rsp.error := False
@ -250,32 +266,43 @@ case class Murax(config : MuraxConfig) extends Component{
addressWidth = 20,
dataWidth = 32
)
val cmdStage = simpleBus.cmd.halfPipe()
val simpleBusStage = SimpleBus()
simpleBusStage.cmd << (if(pipelineApbBridge) simpleBus.cmd.halfPipe() else simpleBus.cmd)
simpleBusStage.rsp >-> simpleBus.rsp
val state = RegInit(False)
cmdStage.ready := False
simpleBusStage.cmd.ready := False
apb.PSEL(0) := cmdStage.valid
apb.PSEL(0) := simpleBusStage.cmd.valid
apb.PENABLE := state
apb.PWRITE := cmdStage.wr
apb.PADDR := cmdStage.address.resized
apb.PWDATA := cmdStage.data
apb.PWRITE := simpleBusStage.cmd.wr
apb.PADDR := simpleBusStage.cmd.address.resized
apb.PWDATA := simpleBusStage.cmd.data
simpleBus.rsp.valid := False
simpleBus.rsp.data := apb.PRDATA
simpleBusStage.rsp.valid := False
simpleBusStage.rsp.data := apb.PRDATA
when(!state){
state := cmdStage.valid
state := simpleBusStage.cmd.valid
} otherwise{
when(apb.PREADY){
state := False
simpleBus.rsp.valid := !cmdStage.wr
cmdStage.ready := True
simpleBusStage.rsp.valid := !simpleBusStage.cmd.wr
simpleBusStage.cmd.ready := True
}
}
}
//Connect the mainBus to all slaves (ram, apbBridge)
val mainBusDecoder = new Area {
def masterBus = mainBus
val masterBus = SimpleBus()
if(!pipelineMainBus) {
masterBus.cmd << mainBus.cmd
masterBus.rsp >> mainBus.rsp
} else {
masterBus.cmd <-< mainBus.cmd
masterBus.rsp >> mainBus.rsp
}
val specification = List[(SimpleBus,SizeMapping)](
ram.bus -> (0x00000000l, onChipRamSize kB),
apbBridge.simpleBus -> (0xF0000000l, 1 MB)

58
src/test/cpp/murax/murax.gtkw
View File

@ -1,21 +1,21 @@
[*]
[*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI
[*] Fri Jul 28 18:56:29 2017
[*] Sat Jul 29 00:24:49 2017
[*]
[dumpfile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/murax/Murax.vcd"
[dumpfile_mtime] "Fri Jul 28 18:50:07 2017"
[dumpfile_size] 141674930
[dumpfile_mtime] "Sat Jul 29 00:24:44 2017"
[dumpfile_size] 177335125
[savefile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/murax/murax.gtkw"
[timestart] 52797277000
[timestart] 56764536000
[size] 1776 953
[pos] -775 -1
*-19.000000 52799592000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[pos] -775 -353
*-19.000000 56765697000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] TOP.
[treeopen] TOP.Murax.
[sst_width] 269
[signals_width] 398
[signals_width] 488
[sst_expanded] 1
[sst_vpaned_height] 279
[sst_vpaned_height] 503
@22
TOP.io_gpioA_read[31:0]
TOP.io_gpioA_writeEnable[31:0]
@ -28,20 +28,18 @@ TOP.Murax.system_mainBus_cmd_payload_data[31:0]
TOP.Murax.system_mainBus_cmd_payload_mask[3:0]
@28
[color] 3
TOP.Murax.system_mainBus_cmd_payload_wr
[color] 3
TOP.Murax.system_mainBus_cmd_valid
[color] 3
TOP.Murax.system_mainBus_cmd_ready
[color] 3
TOP.Murax.system_mainBus_cmd_payload_wr
@22
[color] 3
TOP.Murax.system_mainBus_rsp_payload_data[31:0]
@28
[color] 3
TOP.Murax.system_mainBus_rsp_valid
@29
TOP.Murax.system_ram_bus_cmd_valid
@28
TOP.Murax.system_ram_bus_cmd_ready
@22
TOP.Murax.system_ram_bus_cmd_payload_address[31:0]
@ -55,23 +53,6 @@ TOP.Murax.system_ram_bus_rsp_payload_data[31:0]
TOP.Murax.system_ram_bus_rsp_valid
@22
[color] 1
TOP.Murax.system_apbBridge_bus_cmd_payload_address[31:0]
[color] 1
TOP.Murax.system_apbBridge_bus_cmd_payload_data[31:0]
@28
[color] 1
TOP.Murax.system_apbBridge_bus_cmd_payload_wr
[color] 1
TOP.Murax.system_apbBridge_bus_cmd_ready
[color] 1
TOP.Murax.system_apbBridge_bus_cmd_valid
@22
[color] 1
TOP.Murax.system_apbBridge_bus_rsp_payload_data[31:0]
@28
[color] 1
TOP.Murax.system_apbBridge_bus_rsp_valid
@22
TOP.Murax.system_apbBridge_apb_PADDR[19:0]
@28
TOP.Murax.system_apbBridge_apb_PSEL[0]
@ -84,5 +65,24 @@ TOP.Murax.system_apbBridge_apb_PREADY
TOP.Murax.system_apbBridge_apb_PWDATA[31:0]
@28
TOP.Murax.system_apbBridge_apb_PWRITE
TOP.Murax.system_cpu.DebugPlugin_haltIt
TOP.Murax.system_cpu.DebugPlugin_haltIt
TOP.Murax.system_cpu.decode_arbitration_haltIt
TOP.Murax.system_cpu.execute_arbitration_haltItByOther
TOP.Murax.system_cpu.fetch_arbitration_haltIt
TOP.Murax.system_cpu.memory_arbitration_haltIt
TOP.Murax.system_cpu.prefetch_arbitration_haltIt
TOP.Murax.system_cpu.writeBack_arbitration_haltIt
TOP.Murax.system_cpu.prefetch_IBusSimplePlugin_pendingCmd
@22
TOP.Murax.system_cpu.iBus_cmd_payload_pc[31:0]
@28
TOP.Murax.system_cpu.iBus_cmd_ready
@29
TOP.Murax.system_cpu.iBus_cmd_valid
@22
TOP.Murax.system_cpu.iBus_rsp_inst[31:0]
@28
TOP.Murax.system_cpu.iBus_rsp_ready
[pattern_trace] 1
[pattern_trace] 0